Yes and in practice ARM isn't really RISC and x86 isn't really CISC, with VLIW and pipelines and caches it's more complex. But the original RISC research was i

Yes and in practice ARM isn't really RISC and x86 isn't really CISC, with VLIW and pipelines and caches it's more complex. But the original RISC research was in a time when neither CPU clocks nor memory bandwidth was anywhere near physical limits. It's not the RISC(Apple) is clever and CISC(intel) is a dumb dinosaur - message the article is aiming at.