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TCO is. FGPAs have a fairly high initial outlay, and fairly high costs to program. In addition, they often lag behind CPUs both in density (except for hard IP

by dgacmu 10y ago

TCO is. FGPAs have a fairly high initial outlay, and fairly high costs to program. In addition, they often lag behind CPUs both in density (except for hard IP blocks, but that's not what you're buying them for!) and in frequency. You have to be able to get a big win on parallel execution and avoiding control overhead to make them truly cost-effective. Given that Google's already gone down the custom ASIC path for DNNs (and see Intel's recent acquisition of Nervana for $400m), and how much effort Nvidia is putting into making Pascal a great architecture for deep learning, I'm deeply skeptical of the wins from FPGAs in this space. The volume demands are too high: I suspect they'll fade out pretty quickly in favor of custom silicon.

petra 10y ago
I agree about DNNs. But in general, do you think that FPGA's will become a big part of the cloud ? or will they just be employed in a few, relatively small niches ?
- dgacmu 10y ago
  I don't know, but I'm skeptical. It depends too much on whether the computationally intensive (and latency sensitive) parts of cloud-y workloads become highly specialized, or common. If they're common, you'll just have a set of ASIC-based accelerators, or Intel will start putting in accelerators for them on their chips. This is probably the most likely path. But if it turns out that genomics needs one thing, banking needs another, CAD/design/sim another, etc., then FPGAs might work. Low volume + low money = CPU. Low volume + crazy money -> high frequency trading = FPGAs viable. Low volume + really hard realtime control or fast signal processing -> Often FPGA, but DSPs are still viable. Medium volume + decent money = FPGA. Baidu and MS's deep learning fits here. High volume = ASIC. Google's TPUs fit here. Machine learning and DNNs seem to be in the process of jumping from mostly-CPU to serious ASIC. FPGA's success also depends on how well Intel and the ARM ecosystem can start to support medium-volume customization. Intel's historically been more exclusively high-volume, but if you look at the kinds of deals they're inking with their tier-one (and two?) customers, it's clear they're trying to move in that direction: https://goparallel.sourceforge.net/intel-bets-big-custom-xeon-chips-cloud-companies/ https://goparallel.sourceforge.net/intel-bets-big-custom-xeo... The challenge for FPGAs is that the better the design & synthesis tools get to support FPGA, the easier it is for the CPU manufacturers to do the same thing and adapt more rapidly. The core advantage the FPGAs retain is that they can be retargeted much more easily, and their dev cycle is shorter. My crystal ball is fuzzy. :)
  - petra 10y ago
    Thank you. >> Medium volume + decent money = FPGA. I wonder though: How important is reprogramming ? because you can create structured ASIC's (something between an asic and an FPGA) at a low enough volume( maybe 500/1000+ ,like eAsic(which Intel are working with) ) ?

by dgacmu 10y ago

petra 10y ago

I agree about DNNs. But in general, do you think that FPGA's will become a big part of the cloud ? or will they just be employed in a few, relatively small niches ?

dgacmu 10y ago
I don't know, but I'm skeptical. It depends too much on whether the computationally intensive (and latency sensitive) parts of cloud-y workloads become highly specialized, or common. If they're common, you'll just have a set of ASIC-based accelerators, or Intel will start putting in accelerators for them on their chips. This is probably the most likely path. But if it turns out that genomics needs one thing, banking needs another, CAD/design/sim another, etc., then FPGAs might work. Low volume + low money = CPU. Low volume + crazy money -> high frequency trading = FPGAs viable. Low volume + really hard realtime control or fast signal processing -> Often FPGA, but DSPs are still viable. Medium volume + decent money = FPGA. Baidu and MS's deep learning fits here. High volume = ASIC. Google's TPUs fit here. Machine learning and DNNs seem to be in the process of jumping from mostly-CPU to serious ASIC. FPGA's success also depends on how well Intel and the ARM ecosystem can start to support medium-volume customization. Intel's historically been more exclusively high-volume, but if you look at the kinds of deals they're inking with their tier-one (and two?) customers, it's clear they're trying to move in that direction: https://goparallel.sourceforge.net/intel-bets-big-custom-xeon-chips-cloud-companies/ https://goparallel.sourceforge.net/intel-bets-big-custom-xeo... The challenge for FPGAs is that the better the design & synthesis tools get to support FPGA, the easier it is for the CPU manufacturers to do the same thing and adapt more rapidly. The core advantage the FPGAs retain is that they can be retargeted much more easily, and their dev cycle is shorter. My crystal ball is fuzzy. :)
- petra 10y ago
  Thank you. >> Medium volume + decent money = FPGA. I wonder though: How important is reprogramming ? because you can create structured ASIC's (something between an asic and an FPGA) at a low enough volume( maybe 500/1000+ ,like eAsic(which Intel are working with) ) ?