4 ms·
Or this: module FourInputAndGate(input [3:0] in, output out); assign out = ∈ endmodule Reference: http://www.asic-world.com/verilog/operators
by e19293001 10y ago
Or this:
module FourInputAndGate(input [3:0] in, output out);
assign out = ∈
endmodule
Reference:
http://www.asic-world.com/verilog/operators2.html http://www.asic-world.com/verilog/operators2.html
Really. Hardware is very fascinating.
Great job OP!
- mbad0la 10y agoThis is so cool!