3 ms·

I'm so clueless about a lot of things! :p Can you provide some reference link to systemVerilog?

• orbifold 10y ago
  Here is a link to the standard: http://standards.ieee.org/getieee/1800/download/1800-2012.pdf http://standards.ieee.org/getieee/1800/download/1800-2012.pd... There is an open source compiler which can compile the hardware description subset of system verilog to c++ called verilator: http://www.veripool.org/wiki/verilator http://www.veripool.org/wiki/verilator It was originally developed to verify processor designs at DEC (Alpha etc.). Unfortunately all the other features of system verilog are onl y implemented in commercial tools. I believe the Xilinx Vivado tools support most of it, the others are not really affordable if you are not at an academic institution (Modelsim/the Synopsis tools).
  • mbad0la 10y ago
    Hmm...let's hope that this open-source tool becomes a better alternative to other proprietary softwares. Would be amazing for the academic community. Thanks for the references though!
  • e19293001 10y ago
    In this website[0], you can compile and play with systemverilog using Synopsys' vcs. [0] - https://www.edaplayground.com/ https://www.edaplayground.com/