The output isn't really "passed in". Verilog doesn't have an idea of variables, it replaces what traditionally might be variables with "ports" (think the pins o

The output isn't really "passed in". Verilog doesn't have an idea of variables, it replaces what traditionally might be variables with "ports" (think the pins on a chip). So, input and output ports must all be defined as part of the module declaration. The @(*) syntax is what's called the sensitivity list, it's saying that the state of the module should be recalculated whenever any of the inputs change. Other possible values might include something like @(posedge clk) if you have a clock signal called "clk" and you only want the outputs of the module to update on the rising edge of the clock signal. This is dramatically oversimplifying the insanely complex world of HDL, but it's ultimately not /that/ hard if you know your computer architecture fundamentals.