3 ms·
The equivalent VHDL is: entity ForInpAndGate is port( a: in std_logic; b: in std_logic; c: in std_logic; d: in std_logic;
by TD-Linux 10y ago
The equivalent VHDL is:
entity ForInpAndGate is
port( a: in std_logic;
b: in std_logic;
c: in std_logic;
d: in std_logic;
o: out std_logic;
);
end ForInpAndGate;
architecture behavioral of ForInpAndGate is begin
process(a, b, c, d) begin
o <= a & b & c & d;
end process;
end behavioral;
I don't think it's too much worse, and I do like some features of VHDL, such as it being strongly typed and having typed enums.