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VHDL is really verbose compared to Verilog. Some people love that verbosity, but I prefer to see more "action" in a screen of code.
by blackguardx 10y ago
VHDL is really verbose compared to Verilog. Some people love that verbosity, but I prefer to see more "action" in a screen of code.
- mbad0la 10y agoTrue. I had VHDL in my 5th semester and it was easy to get started with it. Let's hope the community shows some interest in my efforts to make this library the best of both worlds - verbosity with action :P
- blackguardx 10y agoJust curious, why do you like verbosity?
- mbad0la 10y agoI think it's probably a clichéd Js Dev thing :p But one of the reasons might be because I would like the person going through my code to easily understand it without much problems. It's more about perspective I suppose and the requirements of the project.
- TD-Linux 10y agoThe equivalent VHDL is: entity ForInpAndGate is port( a: in std_logic; b: in std_logic; c: in std_logic; d: in std_logic; o: out std_logic; ); end ForInpAndGate; architecture behavioral of ForInpAndGate is begin process(a, b, c, d) begin o <= a & b & c & d; end process; end behavioral; I don't think it's too much worse, and I do like some features of VHDL, such as it being strongly typed and having typed enums.
- nameless912 10y agoSystemVerilog is even cleaner. And those built-in simulation primitives....damn, I loved my SV classes.
- mbad0la 10y agoI'm so clueless about a lot of things! :p Can you provide some reference link to systemVerilog?
- orbifold 10y agoHere is a link to the standard: http://standards.ieee.org/getieee/1800/download/1800-2012.pdf http://standards.ieee.org/getieee/1800/download/1800-2012.pd... There is an open source compiler which can compile the hardware description subset of system verilog to c++ called verilator: http://www.veripool.org/wiki/verilator http://www.veripool.org/wiki/verilator It was originally developed to verify processor designs at DEC (Alpha etc.). Unfortunately all the other features of system verilog are onl y implemented in commercial tools. I believe the Xilinx Vivado tools support most of it, the others are not really affordable if you are not at an academic institution (Modelsim/the Synopsis tools).
- mbad0la 10y agoHmm...let's hope that this open-source tool becomes a better alternative to other proprietary softwares. Would be amazing for the academic community. Thanks for the references though!
- e19293001 10y agoIn this website[0], you can compile and play with systemverilog using Synopsys' vcs. [0] - https://www.edaplayground.com/ https://www.edaplayground.com/