This appears to a global-cache-coherence chip. Slides 12-16 http://insidehpc.com/2016/08/phytium-china-unveils-64-core-arm-hpc-processor/ http://insidehpc.com

This appears to a global-cache-coherence chip. Slides 12-16 http://insidehpc.com/2016/08/phytium-china-unveils-64-core-arm-hpc-processor/ http://insidehpc.com/2016/08/phytium-china-unveils-64-core-a... Each 8-core "panel" has its own L2 and DCU The L3 is globally shared, with the usual cache coherence protocol. 30ns latency for L3 hit. I am not an expert on cache performance, but this certainly seems like an up-to-date design. Can anyone compare this to Xeon and Phi ?!