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Since P6, Intel's CPUs have used a RISC like core with a very heavy decoder that translates x86 CISC instructions to run on the internal ISA. With that in mind

Since P6, Intel's CPUs have used a RISC like core with a very heavy decoder that translates x86 CISC instructions to run on the internal ISA. With that in mind, do older or lesser used instructions actually perform poorly or are they just the wrong choice but actually preferred for other scenarios?

mkup 10y ago
According to [1], on recent Intel CPUs, each instruction is translated by hardware decoder to up to four micro-ops: either trivial micro-ops like addition, subtraction, bitwise and/or/xor, or a special "microcode assist" micro-op which is essentially a function call into the CPU microcode table. According to the same source, CPU microcode table is believed to consist roughly of 20,000 micro-ops which handle edge cases like rare instructions, rare prefixes, FPU denormals, traps/exceptions, all that stuff. Also, CPU microcode table is believed to contain full-blown implementations of RSA and SHA-256 in order to support microcode updates. So, yes, there's a performance gap between instructions with hardware fast path and ones which require a microcode assist. [1] https://eprint.iacr.org/2016/086.pdf https://eprint.iacr.org/2016/086.pdf
- CyberDildonics 10y ago
  The new slides for AMD Zen say explicitly that it has hardware sha256 support.
  - majewsky 10y ago
    Careful. Do they mean an ISA extension to support fast SHA-256 implementations in your code, or do they have a SHA-256 implementation in their microcode for CPU-internal use?
    - CyberDildonics 10y ago
      I don't know and that goes beyond my point. The original poster said that it is rumored that Intel has a full implementation of sha256 in microcode. I am saying that AMD has confirmed that they at least have it in microcode.
dezgeg 10y ago
Yes, for instance the LOOP instruction: http://stackoverflow.com/questions/35742570/why-is-the-loop-instruction-slow-couldnt-intel-have-implemented-it-efficiently http://stackoverflow.com/questions/35742570/why-is-the-loop-...
pkaye 10y ago
Some legacy instructions are too complex and infrequently used so they are microcoded and run much slower.
- PeCaN 10y ago
  Nearly all x86_64 instructions are microcoded on modern Intel and AMD CPUs. That does not mean they're slow. Some instructions may end up slow when the microcode isn't updated to take advantage of the latest processor iteration (I recall this happened to rep movs at some point, which gave it its bad reputation, even though it was fixed). That probably happens often for legacy instructions.
  - gpderetta 10y ago
    No, the large majority of instructions are not microcoded. In addition to microcode having a performance penality by itself, a modern intel cpu machine can decode only one microcoded instruction per cycle, while it normally can decode up to 4 non-microcoded instructions per cycle. Note that microcoding and uop splitting are different things.
    - epsylon 10y ago
      Do you have any reference for most of the stuff you are talking about in the comments here? I'd like to understand it better. Thanks.
      - gpderetta 10y ago
        The bible are Agner Fog optimization manuals [1] which contain quite a detailed description of the microarchitecture of intel and AMD CPUs from the pentium era till today. They are based on the extensive reverse engineering done by the author. David Kanter microarchitecture articles at RWT [2] are also quite good. Intel manuals are quite detailed as well. [1] http://www.agner.org/optimize/ http://www.agner.org/optimize/ [2] http://www.realworldtech.com/cpu/ http://www.realworldtech.com/cpu/
      - 10y ago
klodolph 10y ago
Old instructions may have a smaller encoding, which means it can be hard to tell whether you should use them if they are otherwise slow. The compactness of the x86 instruction encoding is one of the architecture's chief strengths (and weaknesses).
gpderetta 10y ago
> Since P6, Intel's CPUs have used a RISC like core with a very heavy decoder that translates x86 CISC This get repeated often, but it is actually wrong. First of all RISC is a property of the ISA, not the microarchitecture: CISCs have been breaking complex instructions in micro instructions well before the RISC/CISC separation were even conceived. In fact modern CISCs try to not to break instructions until they reach the execution units so that less resources need to be spent tracking them (uop fusion). Some even try to fuse multiple instructions (macro op fusion, many RISCs do it as well).

mkup 10y ago

According to [1], on recent Intel CPUs, each instruction is translated by hardware decoder to up to four micro-ops: either trivial micro-ops like addition, subtraction, bitwise and/or/xor, or a special "microcode assist" micro-op which is essentially a function call into the CPU microcode table. According to the same source, CPU microcode table is believed to consist roughly of 20,000 micro-ops which handle edge cases like rare instructions, rare prefixes, FPU denormals, traps/exceptions, all that stuff. Also, CPU microcode table is believed to contain full-blown implementations of RSA and SHA-256 in order to support microcode updates. So, yes, there's a performance gap between instructions with hardware fast path and ones which require a microcode assist. [1] https://eprint.iacr.org/2016/086.pdf https://eprint.iacr.org/2016/086.pdf

CyberDildonics 10y ago
The new slides for AMD Zen say explicitly that it has hardware sha256 support.
- majewsky 10y ago
  Careful. Do they mean an ISA extension to support fast SHA-256 implementations in your code, or do they have a SHA-256 implementation in their microcode for CPU-internal use?
  - CyberDildonics 10y ago
    I don't know and that goes beyond my point. The original poster said that it is rumored that Intel has a full implementation of sha256 in microcode. I am saying that AMD has confirmed that they at least have it in microcode.

dezgeg 10y ago

Yes, for instance the LOOP instruction: http://stackoverflow.com/questions/35742570/why-is-the-loop-instruction-slow-couldnt-intel-have-implemented-it-efficiently http://stackoverflow.com/questions/35742570/why-is-the-loop-...

pkaye 10y ago

Some legacy instructions are too complex and infrequently used so they are microcoded and run much slower.

PeCaN 10y ago
Nearly all x86_64 instructions are microcoded on modern Intel and AMD CPUs. That does not mean they're slow. Some instructions may end up slow when the microcode isn't updated to take advantage of the latest processor iteration (I recall this happened to rep movs at some point, which gave it its bad reputation, even though it was fixed). That probably happens often for legacy instructions.
- gpderetta 10y ago
  No, the large majority of instructions are not microcoded. In addition to microcode having a performance penality by itself, a modern intel cpu machine can decode only one microcoded instruction per cycle, while it normally can decode up to 4 non-microcoded instructions per cycle. Note that microcoding and uop splitting are different things.
  - epsylon 10y ago
    Do you have any reference for most of the stuff you are talking about in the comments here? I'd like to understand it better. Thanks.
    - gpderetta 10y ago
      The bible are Agner Fog optimization manuals [1] which contain quite a detailed description of the microarchitecture of intel and AMD CPUs from the pentium era till today. They are based on the extensive reverse engineering done by the author. David Kanter microarchitecture articles at RWT [2] are also quite good. Intel manuals are quite detailed as well. [1] http://www.agner.org/optimize/ http://www.agner.org/optimize/ [2] http://www.realworldtech.com/cpu/ http://www.realworldtech.com/cpu/
    - 10y ago

klodolph 10y ago

Old instructions may have a smaller encoding, which means it can be hard to tell whether you should use them if they are otherwise slow. The compactness of the x86 instruction encoding is one of the architecture's chief strengths (and weaknesses).

gpderetta 10y ago

> Since P6, Intel's CPUs have used a RISC like core with a very heavy decoder that translates x86 CISC This get repeated often, but it is actually wrong. First of all RISC is a property of the ISA, not the microarchitecture: CISCs have been breaking complex instructions in micro instructions well before the RISC/CISC separation were even conceived. In fact modern CISCs try to not to break instructions until they reach the execution units so that less resources need to be spent tracking them (uop fusion). Some even try to fuse multiple instructions (macro op fusion, many RISCs do it as well).