4 ms·

The article say Power9 chip will have "hardware assisted garbage collection" and that's all, that's a bit short for such an important topic.. Does anyone have m

by renox 10y ago

The article say Power9 chip will have "hardware assisted garbage collection" and that's all, that's a bit short for such an important topic.. Does anyone have more information about it?

brixon 10y ago
The new SPARCs have something like that too. http://www.mythics.com/about/blog/an-introduction-to-your-servers-next-cpu-the-sparc-m7 http://www.mythics.com/about/blog/an-introduction-to-your-se...
- wepple 10y ago
  > Other silicon accelerators include a SQL coprocessor in each core. Entire SELECT statements now run at silicon speeds. seriously? love to see how/why that was put in the die
  - valarauca1 10y ago
    Oracle did this in the past 2 generations of their UltraSPARC architecture. At it's core a `SELECT FROM` statement is a filter lambda (without any joins, or before/after a join has been done depending on query optimization). Fundamentally this is because an SQL table is a flat array. With row's being flat array's within the table's memory space. Calculating the pointer to fields within rows within a table is ridiculously parallel. You're limited only by SIMD size. (this is 1 FMA + 1 add against a constant ~2 ticks). Also custom wide SIMD registers can allow for `VARCHAR(255)` equality statements to be done in 1 processor cycle.
    - kbenson 10y ago
      I guess I shouldn't be surprised that when a database company swallows a CPU hardware division that the CPU might sprout some more database specific operations, but I was. I would love to see some benchmarks of how much this speeds up some sample workload queries, if you happen to know of some (preferably not from Oracle's marketing dept.)?
      - valarauca1 10y ago
        Oracle UltraSPARC purchasing agreement forbids 3rd party direct comparison benchmarks. The only ones you'll find by 3rd party are non-direct comparisons like transactions per second in Oracle-SQL. Or Core Count.
        kbenson 10y ago
        Why am I not surprised by this. I sometimes find myself thinking I should check my bias against Oracle, just to make sure I'm not being too hard on them for past transgressions (for example, Microsoft is far from perfect but they've come a long ways from many of their more negative past practices). Then I learn something like this, which while it doesn't directly mean they are still continuing in predatory marketing and sales practices, doesn't exactly assuage any fears I might have have had.
        valarauca1 10y ago
        I currently work for a company that heavily uses Oracle technology. It's horrible. Our culmative contracts are worth several hundred thousand dollars per years. But they'll still cheat us on small things. We request information on a training seminar (we had a free attendance voucher), and they lose our account information until 1 week after the seminar ended. It's to the point where I just laugh. Everyone knows their cheating us, but upper management won't change.
        ams6110 10y ago
        Oracle's database is pretty good (if you can afford it). All their other software, from what I've seen, is shockingly bad considering their resources.
        valarauca1 10y ago
        Yes if you shell out for all the money to run it on every core, and use a lot memory it is solid. But the bang for your buck, Microsoft SQL has a better support plan, and saner licensing model. My experience is working with smaller datasets <200GB so YMMV. I mean I'd rather use Postgres. But large corps like having a vendor to call.
  - smegel 10y ago
    Err...you know who bought Sun right?
- kbenson 10y ago
  That's interesting. For some reason, I was under the impression Oracle had basically killed off the hardware development portion of Sun. I don't recall where I got that idea though. Good to see new developments in this line. The more (open) hardware platforms the better, IMO.
  - rbanffy 10y ago
    > I don't recall where I got that idea though. They killed the desktops. That, essentially, made SPARC mostly invisible to most people. They also do a crappy job of reminding the world that a software company (as they position themselves) can make decent hardware.
rch 10y ago
I came here to ask the same thing, did some searching, and still haven't found anything. Edit: Found this in PowerISA_V3.0.pdf Load Doubleword Monitored Instruction: Specifies a new instruction and facility that improves the performance of the garbage collection process and eliminates the need to pause all applications during collection. The ldmx instruction loads the same doubleword in storage as the ldx instruction. ldmx is intended for use by applications when loading data objects during times when objects are being moved as part of a garbage collection process. In this type of usage, all loads of object pointers by applications are performed using ldmx. Whenever objects within a given region of memory are to be moved, the garbage collection program sets the Load Monitored Region registers to encompass the region being moved, and sets BESCRGE LME to 0b11 to enable Load Monitored event-based branches. ...
vertex-four 10y ago
The Reduceron (an FPGA core for running pure functional programs) contains a very simple hardware garbage collector[0]. Almost definitely not the same sort of thing, though.
wmf 10y ago
Presumably it's in here somewhere: http://openpowerfoundation.org/?resource_lib=power-isa-version-3-0 http://openpowerfoundation.org/?resource_lib=power-isa-versi...
- codys 10y ago
  The power ISA specs tend to omit quite a few details about the hardware itself. I wouldn't be surprised if documentation was internal only and the first time we get any details about it is when IBM patches some open source software to take advantage of it.
  - StillBored 10y ago
    They do respond to requests, albeit quite slowly. I wanted documentation to go with some kernel patches they posted to the linux kernel (IOMMU related), that hinted at a mode I was interested in. It took them two years but the docs showed up a few months ago. I suspect I wasn't the only one asking for more detail about system level (or firmware/hypervisor) features that aren't documented in the instruction arch. I think they understand both at the top and the bottom, that the time for hiding stuff like this is over. Pushing it through the immense bureaucracy still takes time but support from upper mgmt eventually gets it done. The one thing IBM has always been good at is documenting their hardware/software. Somewhere in the late 90's they started to hide much of the lowlevel documentation (like the rest of the industry) but I think the slow realization that doing that doesn't help them (or anyone else) is slowly becoming apparent as the most successful companies are frequently the most open ones (and therefor have better linux/open source support). LoPAPR http://openpowerfoundation.org/?resource_lib=linux-on-power-architecture-platform-reference http://openpowerfoundation.org/?resource_lib=linux-on-power-... IODA2 http://openpowerfoundation.org/?resource_lib=openpower-io-design-architecture-ioda-version-2-wg-specification http://openpowerfoundation.org/?resource_lib=openpower-io-de... (although i'm 99% sure the IODA doc is missing a heap of stuff).
nabla9 10y ago
I think it refers to idmix instruction and Load Monitored Region, and Load Monitored Region Registers >The Load Monitored Region registers are used to specify a Load Monitored region, and to specify the sections of the region that are enabled. The Load Monitored region is a contiguous region of storage specified by the Load Monitored Region register. Load Monitored regions range in size from 32 MB to 1 TB. All regions are powers of 2 in length and are aligned (see Section 1.11.1). The Load Monitored region is divided into 64 sections of equal length, each of which can be separately enabled. The Load Monitored Section Enable Register specifies which sections are enabled. >Load Doubleword Monitored Instruction: Specifies a new instruction and facility that improves the performance of the garbage collection process and eliminates the need to pause all applications during collection. Programming Note: >The ldmx instruction loads the same doubleword in storage as the ldx instruction. >Idmx is intended for use by applications when loading data objects during times when objects are being moved as part of a garbage collection process. In this type of usage, all loads of object pointers by applications are performed using ldmx. Whenever objects within a given region of memory are to be moved, the garbage collection program sets the Load Monitored Region registers to encompass the region being moved, and sets BESCR GE LME to 0b11 to enable Load Monitored event-based branches. >Subsequently, if an application program loads (ldmx) a pointer into an enabled section of the Load Monitored region, an event-based branch (EBB) will occur. The EBB handler will load the instruction from storage, and decode the instruction to determine the effective address from which the pointer was loaded. The handler will then load the pointer (obtaining the same value the application obtained), and determine where the corresponding object has been moved to, and update the pointer in storage so that it points to the object's new location. The EBB handler may also take other actions such as updating additional pointers, depending on the situation. After this processing is complete, the EBB handler sets BESCR LME LMEO to (1 0) since the taking of the EBB set these bits to (0,1), and then executes rfebb 1 to re-enable EBBs and return to the application program at the ldmx. The application program re-executes the ldmx, which now returns the updated pointer (which no longer points into an enabled section of the Load Monitored region), and continues. >Other variations and extensions of the above pro- cedure are also possible.
ginko 10y ago
Intel's hugely unsuccessful 432 also supported hardware garbage collection in 1981. https://en.wikipedia.org/wiki/Intel_iAPX_432#Garbage_collection https://en.wikipedia.org/wiki/Intel_iAPX_432#Garbage_collect...
- nickpsecurity 10y ago
  Ok, that makes two of us that read a pile of SW features in HW and thought about the 432. I think this is more like the i960, though, where a fast RISC gets some extra features. Always thought it might have succeeded if not for the BiiN and Ada crap. IBM's been playing it smarter with POWER by making sure its compatible with and aids the software people actually use. So, POWER9 has a much better chance than Intel's prior attempts.

by renox 10y ago

The article say Power9 chip will have "hardware assisted garbage collection" and that's all, that's a bit short for such an important topic.. Does anyone have more information about it?

brixon 10y ago

The new SPARCs have something like that too. http://www.mythics.com/about/blog/an-introduction-to-your-servers-next-cpu-the-sparc-m7 http://www.mythics.com/about/blog/an-introduction-to-your-se...

wepple 10y ago
> Other silicon accelerators include a SQL coprocessor in each core. Entire SELECT statements now run at silicon speeds. seriously? love to see how/why that was put in the die
- valarauca1 10y ago
  Oracle did this in the past 2 generations of their UltraSPARC architecture. At it's core a `SELECT FROM` statement is a filter lambda (without any joins, or before/after a join has been done depending on query optimization). Fundamentally this is because an SQL table is a flat array. With row's being flat array's within the table's memory space. Calculating the pointer to fields within rows within a table is ridiculously parallel. You're limited only by SIMD size. (this is 1 FMA + 1 add against a constant ~2 ticks). Also custom wide SIMD registers can allow for `VARCHAR(255)` equality statements to be done in 1 processor cycle.
  - kbenson 10y ago
    I guess I shouldn't be surprised that when a database company swallows a CPU hardware division that the CPU might sprout some more database specific operations, but I was. I would love to see some benchmarks of how much this speeds up some sample workload queries, if you happen to know of some (preferably not from Oracle's marketing dept.)?
    - valarauca1 10y ago
      Oracle UltraSPARC purchasing agreement forbids 3rd party direct comparison benchmarks. The only ones you'll find by 3rd party are non-direct comparisons like transactions per second in Oracle-SQL. Or Core Count.
      - kbenson 10y ago
        Why am I not surprised by this. I sometimes find myself thinking I should check my bias against Oracle, just to make sure I'm not being too hard on them for past transgressions (for example, Microsoft is far from perfect but they've come a long ways from many of their more negative past practices). Then I learn something like this, which while it doesn't directly mean they are still continuing in predatory marketing and sales practices, doesn't exactly assuage any fears I might have have had.
        valarauca1 10y ago
        I currently work for a company that heavily uses Oracle technology. It's horrible. Our culmative contracts are worth several hundred thousand dollars per years. But they'll still cheat us on small things. We request information on a training seminar (we had a free attendance voucher), and they lose our account information until 1 week after the seminar ended. It's to the point where I just laugh. Everyone knows their cheating us, but upper management won't change.
        ams6110 10y ago
        Oracle's database is pretty good (if you can afford it). All their other software, from what I've seen, is shockingly bad considering their resources.
        valarauca1 10y ago
        Yes if you shell out for all the money to run it on every core, and use a lot memory it is solid. But the bang for your buck, Microsoft SQL has a better support plan, and saner licensing model. My experience is working with smaller datasets <200GB so YMMV. I mean I'd rather use Postgres. But large corps like having a vendor to call.
- smegel 10y ago
  Err...you know who bought Sun right?
kbenson 10y ago
That's interesting. For some reason, I was under the impression Oracle had basically killed off the hardware development portion of Sun. I don't recall where I got that idea though. Good to see new developments in this line. The more (open) hardware platforms the better, IMO.
- rbanffy 10y ago
  > I don't recall where I got that idea though. They killed the desktops. That, essentially, made SPARC mostly invisible to most people. They also do a crappy job of reminding the world that a software company (as they position themselves) can make decent hardware.

rch 10y ago

I came here to ask the same thing, did some searching, and still haven't found anything. Edit: Found this in PowerISA_V3.0.pdf Load Doubleword Monitored Instruction: Specifies a new instruction and facility that improves the performance of the garbage collection process and eliminates the need to pause all applications during collection. The ldmx instruction loads the same doubleword in storage as the ldx instruction. ldmx is intended for use by applications when loading data objects during times when objects are being moved as part of a garbage collection process. In this type of usage, all loads of object pointers by applications are performed using ldmx. Whenever objects within a given region of memory are to be moved, the garbage collection program sets the Load Monitored Region registers to encompass the region being moved, and sets BESCRGE LME to 0b11 to enable Load Monitored event-based branches. ...

vertex-four 10y ago

The Reduceron (an FPGA core for running pure functional programs) contains a very simple hardware garbage collector[0]. Almost definitely not the same sort of thing, though.

wmf 10y ago

Presumably it's in here somewhere: http://openpowerfoundation.org/?resource_lib=power-isa-version-3-0 http://openpowerfoundation.org/?resource_lib=power-isa-versi...

codys 10y ago
The power ISA specs tend to omit quite a few details about the hardware itself. I wouldn't be surprised if documentation was internal only and the first time we get any details about it is when IBM patches some open source software to take advantage of it.
- StillBored 10y ago
  They do respond to requests, albeit quite slowly. I wanted documentation to go with some kernel patches they posted to the linux kernel (IOMMU related), that hinted at a mode I was interested in. It took them two years but the docs showed up a few months ago. I suspect I wasn't the only one asking for more detail about system level (or firmware/hypervisor) features that aren't documented in the instruction arch. I think they understand both at the top and the bottom, that the time for hiding stuff like this is over. Pushing it through the immense bureaucracy still takes time but support from upper mgmt eventually gets it done. The one thing IBM has always been good at is documenting their hardware/software. Somewhere in the late 90's they started to hide much of the lowlevel documentation (like the rest of the industry) but I think the slow realization that doing that doesn't help them (or anyone else) is slowly becoming apparent as the most successful companies are frequently the most open ones (and therefor have better linux/open source support). LoPAPR http://openpowerfoundation.org/?resource_lib=linux-on-power-architecture-platform-reference http://openpowerfoundation.org/?resource_lib=linux-on-power-... IODA2 http://openpowerfoundation.org/?resource_lib=openpower-io-design-architecture-ioda-version-2-wg-specification http://openpowerfoundation.org/?resource_lib=openpower-io-de... (although i'm 99% sure the IODA doc is missing a heap of stuff).

nabla9 10y ago

I think it refers to idmix instruction and Load Monitored Region, and Load Monitored Region Registers >The Load Monitored Region registers are used to specify a Load Monitored region, and to specify the sections of the region that are enabled. The Load Monitored region is a contiguous region of storage specified by the Load Monitored Region register. Load Monitored regions range in size from 32 MB to 1 TB. All regions are powers of 2 in length and are aligned (see Section 1.11.1). The Load Monitored region is divided into 64 sections of equal length, each of which can be separately enabled. The Load Monitored Section Enable Register specifies which sections are enabled. >Load Doubleword Monitored Instruction: Specifies a new instruction and facility that improves the performance of the garbage collection process and eliminates the need to pause all applications during collection. Programming Note: >The ldmx instruction loads the same doubleword in storage as the ldx instruction. >Idmx is intended for use by applications when loading data objects during times when objects are being moved as part of a garbage collection process. In this type of usage, all loads of object pointers by applications are performed using ldmx. Whenever objects within a given region of memory are to be moved, the garbage collection program sets the Load Monitored Region registers to encompass the region being moved, and sets BESCR GE LME to 0b11 to enable Load Monitored event-based branches. >Subsequently, if an application program loads (ldmx) a pointer into an enabled section of the Load Monitored region, an event-based branch (EBB) will occur. The EBB handler will load the instruction from storage, and decode the instruction to determine the effective address from which the pointer was loaded. The handler will then load the pointer (obtaining the same value the application obtained), and determine where the corresponding object has been moved to, and update the pointer in storage so that it points to the object's new location. The EBB handler may also take other actions such as updating additional pointers, depending on the situation. After this processing is complete, the EBB handler sets BESCR LME LMEO to (1 0) since the taking of the EBB set these bits to (0,1), and then executes rfebb 1 to re-enable EBBs and return to the application program at the ldmx. The application program re-executes the ldmx, which now returns the updated pointer (which no longer points into an enabled section of the Load Monitored region), and continues. >Other variations and extensions of the above pro- cedure are also possible.

ginko 10y ago

Intel's hugely unsuccessful 432 also supported hardware garbage collection in 1981. https://en.wikipedia.org/wiki/Intel_iAPX_432#Garbage_collection https://en.wikipedia.org/wiki/Intel_iAPX_432#Garbage_collect...

nickpsecurity 10y ago
Ok, that makes two of us that read a pile of SW features in HW and thought about the 432. I think this is more like the i960, though, where a fast RISC gets some extra features. Always thought it might have succeeded if not for the BiiN and Ada crap. IBM's been playing it smarter with POWER by making sure its compatible with and aids the software people actually use. So, POWER9 has a much better chance than Intel's prior attempts.