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We've got one article ( http://news.ycombinator.com/item?id=123263 http://news.ycombinator.com/item?id=123263 ) in which memory controllers are being brought on
by xirium 19y ago
We've got one article ( http://news.ycombinator.com/item?id=123263 http://news.ycombinator.com/item?id=123263 ) in which memory controllers are being brought on-die to increase speed. We got another article ( http://news.ycombinator.com/item?id=123158 http://news.ycombinator.com/item?id=123158 ) which describes adding another tier of memory controllers to increase throughput.
The latter could be hard to design if you were retro-fitting a tree of pipelined memory controllers and you were concerned about interoperability. However article makes it look like an attempt to bodge extra address lines.
- wmf 19y agoI think it's more about extra chip selects and reducing bus loading. AFAIK, standard DDR2 memory controllers only support so many ranks on the bus, so MetaRAM introduced some muxing to make four or eight ranks look like two. It's a clever hack.