For logic gates there is a "setup" and "hold" time (logic level prior to gate flip, then hold that level) for an operation to be successfully performed and tran

For logic gates there is a "setup" and "hold" time (logic level prior to gate flip, then hold that level) for an operation to be successfully performed and transmitted to the next stage. It should be in the chip's datasheet (if you wanted a precise and specific number). If you don't care about logic transmission and just want "flip" then look at the rise/fall time.