> RISC only made sense when CPU clock speeds were at rough parity with central memory speed, on-chip I-caches were limited, pipelines were short, and compilers

> RISC only made sense when CPU clock speeds were at rough parity with central memory speed, on-chip I-caches were limited, pipelines were short, and compilers were only good at modest optimizations. No, RISC was a response to CPUs becoming faster relative to memory access. Smaller decode logic meant more die space for registers and cache.