3 ms·
> If you look at functionality per instruction byte, RISC is fairly low. You should watch this video: https://www.youtube.com/watch?v=Ii_pEXKKYUg https://www.y
by legulere 10y ago
> If you look at functionality per instruction byte, RISC is fairly low.
You should watch this video: https://www.youtube.com/watch?v=Ii_pEXKKYUg https://www.youtube.com/watch?v=Ii_pEXKKYUg
The most important information therein is that the difference in code density is minuscule between x86, ARM and RISC-V. The differences between GCC versions is even bigger.
> The equations that you have to resolve to issue an X86 instruction are simply more complex than for ARM, and all that bit-flipping consumes power.
It's actually just 3-10% of power consumption [1] and I even heard it claimed that the instruction decoding on ARM is larger than x86
[1] https://www.usenix.org/system/files/conference/cooldc16/cooldc16-paper-hirki.pdf https://www.usenix.org/system/files/conference/cooldc16/cool...
- microcolonel 10y agoAdding to your point; I don't think we can even consider ARM to be a RISC, as Chris Celio is quick to point out in that presentation. It has instructions which are very nearly as complex as x86s, and each year they come closer to having as many as x86 has as well.
- renox 10y ago> I don't think we can even consider ARM to be a RISC, ARMv7 OK, is-it still true with ARMv8? It seems to be a much more 'reduced' ISA.
- microcolonel 10y agoEvery ARMv8 is also an ARMv7; since ARMv8 includes AArch32 in addition to AArch64. It still has Jazelle traps. It also has an 8-byte (though they brag that they only have 4-byte opcodes now) AES round instruction, and a SHA-256 permutation instruction. Admittedly some of AArch64 is much cleaner, it involves fewer new conditional instructions than you would expect for an ARM architecture; however it sure as hell ain't RISC.