NAND gates have two PMOS (pull-up) transistors in parallel and two NMOS (pull-down) transistors in series. This matches well with most CMOS processes, in which

NAND gates have two PMOS (pull-up) transistors in parallel and two NMOS (pull-down) transistors in series. This matches well with most CMOS processes, in which NMOS are faster. NOR gates have two PMOS in series and two NMOS in parallel, so either your pull up time will be significantly longer than your pull down time, or you're going to have to make the PMOS pretty big. None of this really mattered at the time; the Apollo used resistor-transistor logic (RTL), which in turn used bipolar junction transistors (BJTs) instead of the CMOS (C is for complementary, meaning NMOS and PMOS) used for most digital logic today. In RTL (there are analogous logic families using CMOS too), instead of having a pull-up network of transistors, there is a weak pull-up resistor that makes the output high by default, unless it is pulled down by a network of (usually NPN) BJTs. In the case of an RTL NOR gate, it is just a bunch of NPN BJTs in parallel for the pull-down network, so it's pretty efficient ( http://www.play-hookey.com/digital/experiments/rtl_nor4.html http://www.play-hookey.com/digital/experiments/rtl_nor4.html ). Sorry for the longish post.