No, Intel CPUs are optimized to simulate CPUs Some stories from back around 2000 when designing CPUs at Intel. Some people did bemoan the fact the few software

No, Intel CPUs are optimized to simulate CPUs Some stories from back around 2000 when designing CPUs at Intel. Some people did bemoan the fact the few software actually needed the performance in the processors we were building. One of the benchmarks where the performance is actually needed was ripping DVDs. That lead to the unofficial saying "The future of CPU performance is in copyright infringement." (Not seriously, mind you) However, here is a case where the CPUs were actually modified to improve one certain program. From: https://www.cs.rice.edu/~vardi/comp607/bentley.pdf https://www.cs.rice.edu/~vardi/comp607/bentley.pdf (section 2.3) "We ran these simulation models on either interactive workstations or compute servers – initially, these were legacy IBM RS6Ks running AIX, but over the course of the project we transitioned to using mostly Pentium® III based systems running Linux. The full-chip model ran at speeds ranging from 05-0.6 Hz on the oldest RS6K machines to 3-5 Hz on the Pentium® III based systems (we have recently started to deploy Pentium® 4 based systems into our computing pool and are seeing full-chip SRTL model simulation speeds of around 15 Hz on these machines)" You can see that the P6-based processors (PIII) were a lot faster than the RS6K's and the Wmt version (P4) was faster still? That program is csim and it is a program that does a really dumb translation of the SRTL model of the chip (think verilog) to C code that then gets compiled with GCC. (the Intel compiler choked) That code was huge and it had loops with 2M basic blocks. It totally didn't fit in any instruction cache for processors. Most processors assume they are running from the instruction cache and stall when reading from memory. Since running csim is one of the testcases we used when evaluating performance the frontend was designed to execute directly from memory. The frontend would pipeline cacheline fetches from memory which the decoders would unpack in parallel. It could execute at the memory read bandwidth. This was improved more on Wmt. This behavior probably helps some other read programs now, but at the time this was the only case we saw where it really mattered. The end of the section is unrelated but fun: "By tapeout we were averaging 5-6 billion cycles per week and had accumulated over 200 billion (to be precise, 2.384 * 1011) SRTL simulation cycles of all types. This may sound like a lot, but to put it into perspective, it is roughly equivalent to 2 minutes on a single 1 GHz CPU!" Games were important but at the time most of the performance came from the graphics card. In recent years Intel has improved the on-chip graphics and offloaded some of the 3d work to the processor using these vector extensions. That is to reclaim the money going to the graphic card companies.