All kinds of architectures and algorithms can be implemented at the chip level in silicon. But, until recently, the "just make a faster Von Neumann machine" sch

All kinds of architectures and algorithms can be implemented at the chip level in silicon. But, until recently, the "just make a faster Von Neumann machine" school of chip design has always beaten the "make a task optimized chip" school. Is there a similar tension of the deign of Q-computers? Can we make an educated guess on which design school will dominate?