4 ms·
And of those that map to implementations, many are physically infeasible implementations
by sliverstorm 10y ago
And of those that map to implementations, many are physically infeasible implementations
- akiselev 10y agoAnd the designs that are feasibly synthesizable usually have to be tweaked until the timing works out, which gets harder the faster your clock speed and the more different clock/power domains you have. There's a significant risk that any high level abstraction would be leaky enough that you might have to rip up large parts of the design and start from scratch with Verilog/HDL anyway.
- deleted 10y ago[deleted]