4 ms·

The current pipeline for such a request would be the GPU sending a request for more data, the CPU receiving it, the kernel figuring out who should handle the re

The current pipeline for such a request would be the GPU sending a request for more data, the CPU receiving it, the kernel figuring out who should handle the request, the handler then making a request to the kernel for the data on the SSDs, the SSDs sending the data back to main memory, the kernel telling the handler where the memory is, then the handler telling the kernel to send the memory to the video card. In contrast, the route with the on-board SSDs is that the GPU makes the request, the ASIC that handles NVMe requesting from the memory chips, the memory chips sending to the ASIC, which goes into memory. There are a lot fewer steps there, and a lot fewer places where delayed interrupts, etc can introduce lag.

protomok 10y ago
With DMA and the fact that the GPU is a PCIE bus master I don't expect much userland/kernel/interrupt activity...here is my naive implementation of "traditional" 8k video streaming: (CPU) WHILE video not done 1 - Initiate DMA from SSD -> main memory with some large (say 128MB) chunk of 8k video 2 - Signal GPU to begin DMA transfer 3 - Wait for interrupt from GPU (GPU) WHILE video not done 1 - Wait for CPU to indicate data is ready 2 - Initiate DMA from main memory -> local GPU memory over PCIE 3.0 x16 link 3 - Issue interrupt to CPU 4 - Render chunk of video