5 ms·

Note that they bury an important concept deeper in the article: The new report embraces these trends, predicting an end to traditional scaling—the shrinking of

Note that they bury an important concept deeper in the article: The new report embraces these trends, predicting an end to traditional scaling—the shrinking of chip features—by the early 2020’s. But the idea that we’re now facing an end to Moore’s Law “is completely wrong,” Gargini says. ... If a company really wanted to, Gargini says, it could continue to make transistors smaller well into the 2020s, “but it’s more economic to go 3-D. That’s the message we wanted to send.”

tim333 10y ago
Moore's law has always been down to economics - it was worth the industry's investment to develop more transistors per chip area for the next year. If that stops then it stops. Computers will keep getting faster and more powerful though by whatever means makes economic sense.
- ghshephard 10y ago
  Right - but the subtle, and easy to miss message here, isn't that its not longer possible, or even economical to continue to increase density of transistors absent other opportunities, but that with the advent of 3D technologies, increasing the number of transistors per chip can be done more efficiently using 3D approaches. It may be, that once that approach has run it's course, the industry switches back to increasing density again.
  - ci5er 10y ago
    Ultimately you hit a 2D density wall. I'd imagine it's harder to get more dense than one bit per several atoms. A silicon atom itself is 0.2nm, so ... not that far off of where we already are. That pretty much maxes out the thin-film 2D approach, and to pack in more, we'll need to go vertical. And to do that, we'll need to create novel fabrication technologies (unless they come up with some photo-lithography magic that I can't imagine right now), and, problematically, they'll need to deal with heat. This is not to say that I am disagreeing with you on the switch-back-to-2d front, but I don't think we have much further to go on the 2d-density front.
    - deleted 10y ago
      [deleted]
    - ghshephard 10y ago
      Completely concur with you. The ITRS reports indicate that if 3D integration hadn't become the new mechanism for increasing transistor density, that gate-length reduction cycle would have run out of gas around 2028 - so about 12 years out regardless. It remains to be seen we still have that 12 years of efficiency available to us after building 3D chips. I can easily imagine that heat distribution would be a real problem.
      - ci5er 10y ago
        > I can easily imagine that heat distribution would be a real problem. Given how much of a problem it already is in 2D where the entire die area simply radiates "up and out", I think that head might be the real problem. I don't know how one would build a 3D embedded heat-sink, you know, something like this with the transistors and and connective mesh all around [1]. Maybe it looks like a Menger sponge [2], but that looks tough too! :-) [1] https://s3.amazonaws.com/s3-blogs.mentor.com/robinbornoff/files/2015/03/DHS1.png https://s3.amazonaws.com/s3-blogs.mentor.com/robinbornoff/fi... [2] https://en.wikipedia.org/wiki/Menger_sponge https://en.wikipedia.org/wiki/Menger_sponge
        petra 10y ago
        First we need to cool the chips. We can increase cooling rate, using micro channels that carry water. Darpa verified that we can increase it to "1 kW/cm2 die-level heat flux with multiple local 30 kW/cm2 hot spots. This is about four to five times more heat per unit area than most current chips dissipate"[1]. Maybe we can do even better. The thing is - it's expensive. But than we can use this to build logic with memory on top ,and get huge bandwidth - and in multicore systems you could 100x performance in some algorithms , with easier programming. But this will be expensive. But than we could start using those systems, building an ecosystem around them, generate money - and slowly, generation by generation with a moore's law like race, work on building photonics to greatly decrease power consumption - and hence cost. That's at least the plan in [2]. Also relevant: ST microelectronics is in the final stages of opening a leading edge, commercial photonics fab. [1]https://www.helpnetsecurity.com/2016/03/11/microfluidic-cooling/ https://www.helpnetsecurity.com/2016/03/11/microfluidic-cool... [2]http://drum.lib.umd.edu/handle/1903/17153 http://drum.lib.umd.edu/handle/1903/17153
  - xenadu02 10y ago
    Actually it will soon be physically impossible to continue 2D scaling. Even if you could operate a single-atom gate once you hit that limit you're done. We aren't that far away.
  - Animats 10y ago
    Not more efficiently. 3D here means running the IC through more fab steps to stack layers. This raises costs, which are roughly linear with the number of fab steps. It also hurts yield, although memory devices can be designed to tolerate errors. 3D stacking is mostly useful for parts that don't generate much heat. The inner layers have cooling problems. Flash memory, yes; CPUs, no. Moore's Law was about increasing area density of transistors on a chip. Transistors got smaller and faster. Fabs got more expensive at each shrink, though. For a long time, the cost advantages of the shrink were a win over the increased fab cost. But that's ended. Fab cost ended up dominating the industry. There are only four high-end fab companies left. The question for years is which limit would dominate - fab cost, heat dissipation, or, ultimately, the size of atoms and electrons. The first two are being reached now. Flash devices are already down to 10-20 significant electrons per storage cell, so there's not much room left there. Atoms, electrons, and photons are just too big. There's no longer plenty of room at the bottom, as Feynman put it.
    - ghshephard 10y ago
      More efficiently in the sense that, on a ROI basis, there's now more R on the I of 3D stacking, than there is in the I of increasing transistor density. Agreed that Moore's law was about increasing density of transistors on a chip - but you can do that in various ways. The article was clear to state, "Moore’s Law, he emphasizes, is simply a prediction about how many transistors can fit in a given area of IC—whether it’s done, as it has been for decades, in a single layer or by stacking multiple layers."

tim333 10y ago

Moore's law has always been down to economics - it was worth the industry's investment to develop more transistors per chip area for the next year. If that stops then it stops. Computers will keep getting faster and more powerful though by whatever means makes economic sense.

ghshephard 10y ago
Right - but the subtle, and easy to miss message here, isn't that its not longer possible, or even economical to continue to increase density of transistors absent other opportunities, but that with the advent of 3D technologies, increasing the number of transistors per chip can be done more efficiently using 3D approaches. It may be, that once that approach has run it's course, the industry switches back to increasing density again.
- ci5er 10y ago
  Ultimately you hit a 2D density wall. I'd imagine it's harder to get more dense than one bit per several atoms. A silicon atom itself is 0.2nm, so ... not that far off of where we already are. That pretty much maxes out the thin-film 2D approach, and to pack in more, we'll need to go vertical. And to do that, we'll need to create novel fabrication technologies (unless they come up with some photo-lithography magic that I can't imagine right now), and, problematically, they'll need to deal with heat. This is not to say that I am disagreeing with you on the switch-back-to-2d front, but I don't think we have much further to go on the 2d-density front.
  - deleted 10y ago
    [deleted]
  - ghshephard 10y ago
    Completely concur with you. The ITRS reports indicate that if 3D integration hadn't become the new mechanism for increasing transistor density, that gate-length reduction cycle would have run out of gas around 2028 - so about 12 years out regardless. It remains to be seen we still have that 12 years of efficiency available to us after building 3D chips. I can easily imagine that heat distribution would be a real problem.
    - ci5er 10y ago
      > I can easily imagine that heat distribution would be a real problem. Given how much of a problem it already is in 2D where the entire die area simply radiates "up and out", I think that head might be the real problem. I don't know how one would build a 3D embedded heat-sink, you know, something like this with the transistors and and connective mesh all around [1]. Maybe it looks like a Menger sponge [2], but that looks tough too! :-) [1] https://s3.amazonaws.com/s3-blogs.mentor.com/robinbornoff/files/2015/03/DHS1.png https://s3.amazonaws.com/s3-blogs.mentor.com/robinbornoff/fi... [2] https://en.wikipedia.org/wiki/Menger_sponge https://en.wikipedia.org/wiki/Menger_sponge
      - petra 10y ago
        First we need to cool the chips. We can increase cooling rate, using micro channels that carry water. Darpa verified that we can increase it to "1 kW/cm2 die-level heat flux with multiple local 30 kW/cm2 hot spots. This is about four to five times more heat per unit area than most current chips dissipate"[1]. Maybe we can do even better. The thing is - it's expensive. But than we can use this to build logic with memory on top ,and get huge bandwidth - and in multicore systems you could 100x performance in some algorithms , with easier programming. But this will be expensive. But than we could start using those systems, building an ecosystem around them, generate money - and slowly, generation by generation with a moore's law like race, work on building photonics to greatly decrease power consumption - and hence cost. That's at least the plan in [2]. Also relevant: ST microelectronics is in the final stages of opening a leading edge, commercial photonics fab. [1]https://www.helpnetsecurity.com/2016/03/11/microfluidic-cooling/ https://www.helpnetsecurity.com/2016/03/11/microfluidic-cool... [2]http://drum.lib.umd.edu/handle/1903/17153 http://drum.lib.umd.edu/handle/1903/17153
- xenadu02 10y ago
  Actually it will soon be physically impossible to continue 2D scaling. Even if you could operate a single-atom gate once you hit that limit you're done. We aren't that far away.
- Animats 10y ago
  Not more efficiently. 3D here means running the IC through more fab steps to stack layers. This raises costs, which are roughly linear with the number of fab steps. It also hurts yield, although memory devices can be designed to tolerate errors. 3D stacking is mostly useful for parts that don't generate much heat. The inner layers have cooling problems. Flash memory, yes; CPUs, no. Moore's Law was about increasing area density of transistors on a chip. Transistors got smaller and faster. Fabs got more expensive at each shrink, though. For a long time, the cost advantages of the shrink were a win over the increased fab cost. But that's ended. Fab cost ended up dominating the industry. There are only four high-end fab companies left. The question for years is which limit would dominate - fab cost, heat dissipation, or, ultimately, the size of atoms and electrons. The first two are being reached now. Flash devices are already down to 10-20 significant electrons per storage cell, so there's not much room left there. Atoms, electrons, and photons are just too big. There's no longer plenty of room at the bottom, as Feynman put it.
  - ghshephard 10y ago
    More efficiently in the sense that, on a ROI basis, there's now more R on the I of 3D stacking, than there is in the I of increasing transistor density. Agreed that Moore's law was about increasing density of transistors on a chip - but you can do that in various ways. The article was clear to state, "Moore’s Law, he emphasizes, is simply a prediction about how many transistors can fit in a given area of IC—whether it’s done, as it has been for decades, in a single layer or by stacking multiple layers."