3 ms·
In this talk https://news.ycombinator.com/item?id=12101908 https://news.ycombinator.com/item?id=12101908 they said their toolchain can output layouts for the CP
by tlrobinson 10y ago
In this talk https://news.ycombinator.com/item?id=12101908 https://news.ycombinator.com/item?id=12101908 they said their toolchain can output layouts for the CPU on silicon, and it would cost about $25,000 to have photomasks made, and I think about $0.50 per chip.
- analognoise 10y agoI haven't seen that part of their toolchain; that's where I'm interested. Also, seeing a successful test of this toolchain in working silicon, with a known vendor and a good process, would be extremely helpful for the community (if other people are going to get aboard, which I hope they are).
- nickpsecurity 10y agoLook up Qflow open-source flow. It's the likely toolchain OSS projects will use. Combines Yosys front-end, ABC backend, and custom tool (Qrouter) for routing. Worth evaluating.
- analognoise 10y agoYosys is a Verilog front-end; this is being designed in VHDL. It looks like there is a translator, but I'm unsure about its license, source availability, and capability.