Target: 28nm, 4x 1GHz+ application cores, ~8 minion cores (see http://www.lowrisc.org/docs/memo-2014-001-tagged-memory-and-minion-cores/ http://www.lowrisc.org/

Target: 28nm, 4x 1GHz+ application cores, ~8 minion cores (see http://www.lowrisc.org/docs/memo-2014-001-tagged-memory-and-minion-cores/ http://www.lowrisc.org/docs/memo-2014-001-tagged-memory-and-...), tagged memory, USB, LPDDR3. For more detailed specs, that's going to depend on confirming those details and the package design. Our aim is open source to the RTL. Open analog IP (e.g. the DDR PHY and USB PHY) is a much more difficult proposition - it's process specific, and reliant on NDAed/trade secret details of the particular process making redistribution difficult. Therefore, we will use existing commercial PHYs, and it may make sense initially to use the standard proprietary controller it has been verified against. Over the long term, as I say, we'd like all RTL to be open but you've got to start somewhere. I think there's a parallel to the early days of GNU where they worked on replacing UNIX components piece by piece. It would be great if we could share the place+routed design at zero cost to anyone with the appropriate agreement with the fab.