The problem is that macro-op fusion, at least as commonly implemented, requires instructions to be adjacent, or at least close, for fusion to happen. This mean

The problem is that macro-op fusion, at least as commonly implemented, requires instructions to be adjacent, or at least close, for fusion to happen. This means that your careful plan of "not designing the µarch into the ISA" effectively goes out the window. It's not literally in the ISA, but the compiler needs to order the instructions just so to benefit from the fusion opportunities of the µarch that it's targeting, which often penalizes low-power designs that don't have the fusion in question. There are some sequences where it makes an enormous amount of sense (cmp+jcc, mulhi+mullo, etc); most sufficiently complex µarchs already do those. RISC-V isn't magically going to squeeze a lot more macro-fusion opportunities out that other architectures aren't able to take advantage of.