4 ms·

I've always wondered why a CISC architecture like x86 didn't include a CLR instruction...

• Annatar 10y ago
  On some processor families, like for instance the MC68000 family of processors, the clr instruction always wastes at least one clock cycle reading the register being cleared before actually clearing it, which is why when you look at the assembler code for that processor family, you will rarely see the clr instruction being used: http://www.easy68k.com/paulrsm/doc/trick68k.htm http://www.easy68k.com/paulrsm/doc/trick68k.htm common tricks to clear out a data register on the 68000 family in a performant way include: moveq #0, d0 ; this works because zero can be expressed with only seven bits eor.l d0, d0 sub.l d0, d0 and for the address register sub.l a0, a0 eor.l a0, a0