> Yes, but this particular CPU/SoC has a parallel bus with the NAND flash connected to it. Which would be the more traditional way to connect an FPGA. Absolute

> Yes, but this particular CPU/SoC has a parallel bus with the NAND flash connected to it. Which would be the more traditional way to connect an FPGA. Absolutely. > As one can (typically) configure very relaxed timings on these busses, it's much, much easier to interface to and sufficient for everything that doesn't have to be super-fast. "super-fast" is probably the keyword here. In an oscilloscope you normally want a very short trigger re-arm interval. Which means that you want to get the data out of the acquisition buffer as fast as possible. At the sampling rates the used ADC supports the regular parallel bus timings might be to slow, but by implementing a DDR2 interface a very quick transfer could be implemented. Actually if I had to design this (actually only recently I did design something like this) I'd not transfer acquired samples to main system memory at all but instead present the FPGA attached DDR2 to the SoC in a double buffered manner and even do things like averaging, envelope tracking and similar acquisition tasks in FPGA on the backbuffer memory.