4 ms·

Thanks for the explanation. In the x86 code, is there an advantage of using the xor instead of a load/mov? Is it to avoid a fetch? (I programmed 6502/6510 as

by KSS42 10y ago

Thanks for the explanation. In the x86 code, is there an advantage of using the xor instead of a load/mov? Is it to avoid a fetch? (I programmed 6502/6510 assembly as a kid, but have no experience with x86 assembly)

CJefferson 10y ago
The xor is shorter.
strangecasts 10y ago
Yeah, it's shorter and it doesn't touch any other registers.
alblue 10y ago
The encoding of the machine instruction is 2 bytes for xor eax,eax - if you were doing a load/mov then you'd have to use a numeric cknstant which would be 4 bytes to represent zero and then more for the mov itself. In addition when you have dependent loads of registers between instructions you can end up with pipeline stalls that delay the instruction (even if it shouldn't have any logical effect). The xor pattern is so common that inside the processor (which translates isa instructions to microcode) recognise it explicitly and so it's treated as a special case. In fact no xor happens and the register is simply reprinted to a fresh value containing zero.
- 13of40 10y ago
  I've always wondered why a CISC architecture like x86 didn't include a CLR instruction...
  - Annatar 10y ago
    On some processor families, like for instance the MC68000 family of processors, the clr instruction always wastes at least one clock cycle reading the register being cleared before actually clearing it, which is why when you look at the assembler code for that processor family, you will rarely see the clr instruction being used: http://www.easy68k.com/paulrsm/doc/trick68k.htm http://www.easy68k.com/paulrsm/doc/trick68k.htm common tricks to clear out a data register on the 68000 family in a performant way include: moveq #0, d0 ; this works because zero can be expressed with only seven bits eor.l d0, d0 sub.l d0, d0 and for the address register sub.l a0, a0 eor.l a0, a0
- Someone 10y ago
  For those that want more details, there's https://randomascii.wordpress.com/2012/12/29/the-surprising-subtleties-of-zeroing-a-register/ https://randomascii.wordpress.com/2012/12/29/the-surprising-...

by KSS42 10y ago

CJefferson 10y ago

The xor is shorter.

strangecasts 10y ago

Yeah, it's shorter and it doesn't touch any other registers.

alblue 10y ago

The encoding of the machine instruction is 2 bytes for xor eax,eax - if you were doing a load/mov then you'd have to use a numeric cknstant which would be 4 bytes to represent zero and then more for the mov itself. In addition when you have dependent loads of registers between instructions you can end up with pipeline stalls that delay the instruction (even if it shouldn't have any logical effect). The xor pattern is so common that inside the processor (which translates isa instructions to microcode) recognise it explicitly and so it's treated as a special case. In fact no xor happens and the register is simply reprinted to a fresh value containing zero.

13of40 10y ago
I've always wondered why a CISC architecture like x86 didn't include a CLR instruction...
- Annatar 10y ago
  On some processor families, like for instance the MC68000 family of processors, the clr instruction always wastes at least one clock cycle reading the register being cleared before actually clearing it, which is why when you look at the assembler code for that processor family, you will rarely see the clr instruction being used: http://www.easy68k.com/paulrsm/doc/trick68k.htm http://www.easy68k.com/paulrsm/doc/trick68k.htm common tricks to clear out a data register on the 68000 family in a performant way include: moveq #0, d0 ; this works because zero can be expressed with only seven bits eor.l d0, d0 sub.l d0, d0 and for the address register sub.l a0, a0 eor.l a0, a0
Someone 10y ago
For those that want more details, there's https://randomascii.wordpress.com/2012/12/29/the-surprising-subtleties-of-zeroing-a-register/ https://randomascii.wordpress.com/2012/12/29/the-surprising-...