I believe this [1] is what you are referencing. Additional reading for the truly knowledge craving [2] (section 3.7.6). For the lazy: On aligned data REP MOVS

I believe this [1] is what you are referencing. Additional reading for the truly knowledge craving [2] (section 3.7.6). For the lazy: On aligned data REP MOVS will automatically select the largest available register/load/store instruction to use. So invoking this instruction will also determine SSE2 vs AVX vs AVX512 (or more over its burned into the silicon). Furthermore if your allocation is large enough it will by-pass caching mechanisms for an additional speed up. For the VERY lazy: REP MOVS will attempt to saturate DRAM bandwidth. The best hand coded ASM or C can hope to do is be as fast as it. [1] https://stackoverflow.com/questions/26246040/whats-missing-sub-optimal-in-this-memcpy-implementation https://stackoverflow.com/questions/26246040/whats-missing-s... [2] https://www-ssl.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html https://www-ssl.intel.com/content/www/us/en/architecture-and...