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I don't completely agree that fabbing a chip is "prohibitively expensive and insanely work-intensive." While it's not cheap, lots of university projects fab chi
by jeffbush 10y ago
I don't completely agree that fabbing a chip is "prohibitively expensive and insanely work-intensive." While it's not cheap, lots of university projects fab chips using multi project wafer services. For example, the Rocket core from Berkeley has been taped out 11 times: https://www.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html https://www.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-1... and can boot Linux.
But, I agree with your point that a simulator is a much easier step that gets most of the data.
- kristianp 10y agoAnother example is the kilocore cpu in the news last month: https://www.ucdavis.edu/news/worlds-first-1000-processor-chip https://www.ucdavis.edu/news/worlds-first-1000-processor-chi...
- cfallin 10y agoFair point -- I forgot about MOSIS. Agreed, pretty reasonable for small test runs. I guess I've mostly heard of tapeouts when proving out a full design though, e.g. TRIPS from UT-Austin (and they had a team of ~20 students, so that was worth a number of dissertations). I can't imagine doing a tapeout while working on caching or branch prediction or other core comparch subfields like that -- the deliverable is an algorithm and/or a new idea, not a physical proof of concept, and the usual effort (a grad-student-year or two, at most) isn't high enough. (All that said, seeing a real chip at the end of a project must be a heck of an exhilarating feeling of success...)
- russdill 10y agoEven companies worth billions that have their own fab simulate the chip first before fabbing it to test it and benchmark it.
- majewsky 10y agoExactly. For a primary source, see this talk from 32C3 where an AMD CPU designer explained their process in detail: https://media.ccc.de/v/32c3-7171-when_hardware_must_just_work https://media.ccc.de/v/32c3-7171-when_hardware_must_just_wor...