3 ms·
The inefficiency you are talking about is not due to the fact that there is a synchronous clock (within each individual "block", since there needs to be some as
by trsohmers 10y ago
The inefficiency you are talking about is not due to the fact that there is a synchronous clock (within each individual "block", since there needs to be some async logic going between the different clock domains of DRAM and the processor). The waste in getting numbers from RAM to the register file is primarily due to the hardware managed cache hierarchy, which we are addressing at REX Computing, along with John Gustafson as an advisor.
- sliverstorm 10y agoWaste? Or overhead in exchange for having a cache?
- trsohmers 10y agoObviously tooting my own horn here, but our solution is replacing hardware managed caches with software managed caches... You get to have larger, lower latency "caches" of SRAM in our solution, that also use less power in moving data from RAM to the register file through them since we very granularly control the hierarchy.