3 ms·

I said the same thing a year ago when I had FPGA synthesized verilog and decided to go get a real chip made. Closing timing along with optimizing for PPA for an

I said the same thing a year ago when I had FPGA synthesized verilog and decided to go get a real chip made. Closing timing along with optimizing for PPA for an ASIC vs an FPGA is a royal PITA. And that's just on the front end design work... A core on a FPGA gives you no real idea when it comes to placement or all of the other hurdles of the backend flow of a real ASIC! We ended up re doing everything (which overall was a good thing, as we made a lot better decisions from the beginning by redesigning), but that's show biz.

jhallenworld 10y ago
This used to be Altera's "Hardcopy" advantage: an easy gate-array version of their FPGAs could (in theory) be made because: 1. the gate array uses the same gates as the FPGA, just the interconnect is customized. 2. Use Primetime compatible timing constraints for the FPGA design to begin with.
- trsohmers 10y ago
  While obviously better than just the FPGA, it is still very inefficient compared to a real ASIC. Altera and Xilinx both stopped offering their programs in this area due to the fact that it as it is not really cost effective to have the same transistor level mask set and then have to buy all new masks on top once you get to sub 28nm processes. As for primetime, we use Synopsys Synplify Pro for FPGA synthesis, and while it does a better job than Altera/Xilinx's tools, it does no where near as well (and works very differently) compared ot physical aware synthesis from Design Compiler or RC/Genus.
  - jhallenworld 10y ago
    Primetime is just the timing checker.. where the syntax for sdc files originated I think. We found that Synplify Pro is not quite as good as the vendor tools (xst/quartus) for FPGA synthesis, but I've not compared them recently. Actually there used to be a version of DC for FPGAs, but it was not good at all. I think it was not as prepared to duplicate logic or flops as compared with the FPGA specific tools.

jhallenworld 10y ago

This used to be Altera's "Hardcopy" advantage: an easy gate-array version of their FPGAs could (in theory) be made because: 1. the gate array uses the same gates as the FPGA, just the interconnect is customized. 2. Use Primetime compatible timing constraints for the FPGA design to begin with.

trsohmers 10y ago
While obviously better than just the FPGA, it is still very inefficient compared to a real ASIC. Altera and Xilinx both stopped offering their programs in this area due to the fact that it as it is not really cost effective to have the same transistor level mask set and then have to buy all new masks on top once you get to sub 28nm processes. As for primetime, we use Synopsys Synplify Pro for FPGA synthesis, and while it does a better job than Altera/Xilinx's tools, it does no where near as well (and works very differently) compared ot physical aware synthesis from Design Compiler or RC/Genus.
- jhallenworld 10y ago
  Primetime is just the timing checker.. where the syntax for sdc files originated I think. We found that Synplify Pro is not quite as good as the vendor tools (xst/quartus) for FPGA synthesis, but I've not compared them recently. Actually there used to be a version of DC for FPGAs, but it was not good at all. I think it was not as prepared to duplicate logic or flops as compared with the FPGA specific tools.