I need to read what you've said regarding simulations and pseudotime, but I've been wondering if this is along the same lines has as an HDL like VHDL/Verilog/Sy

I need to read what you've said regarding simulations and pseudotime, but I've been wondering if this is along the same lines has as an HDL like VHDL/Verilog/SystemVerilog. I do chip implementations in those languages, which of course involves simulation and a time concept. I get the idea that is not the sort of simulation you mean, but I'm not sure. The other thought I had was simulation more in the SPICE sense that iterate toward a solution in steps. Any chance you could briefly clarify, and/or toss out a resource that points in the right direction?