5 ms·

Does anyone have a link or the name of another weird architecture that was posted a while ago? (~3 months maybe?) I remember that there were a large number of c

by foota 10y ago

Does anyone have a link or the name of another weird architecture that was posted a while ago? (~3 months maybe?) I remember that there were a large number of cores that all communicated with each other in some weird way and that they like didn't have main system memory or something like that...

jacquesm 10y ago
Sutherlands 'Fleet'?
- foota 10y ago
  Doesn't look like it... there was an established website for the project. It seemed to have some big names from processor design and such behind it as well (at least from what I gathered on their wikipedia pages ;) ) For future reference, here is a link talking about the arch mentioned so that no one else has to wade through google's results for "fleet architecture": http://arc.cecs.pdx.edu/publications http://arc.cecs.pdx.edu/publications edit: previous (2009) discussion about fleet: https://news.ycombinator.com/item?id=723882 https://news.ycombinator.com/item?id=723882
  - jacquesm 10y ago
    That one?: https://news.ycombinator.com/item?id=11845698 https://news.ycombinator.com/item?id=11845698
elij 10y ago
Maybe this? https://news.ycombinator.com/item?id=11845698 https://news.ycombinator.com/item?id=11845698
- foota 10y ago
  No :/ Thank you both for your suggestions though, they are appreciated :) If it helps it had the same sort of feel as the Mill architecture, in that it was a small project being developed by very enthusiastic people.
  - dnautics 10y ago
    Rex computing neo chip? I know the founders and did a bit of contract work (virtual hve) on it and I think they wouldn't like being compared to mill :)
jsnell 10y ago
Could be a number of things. The Connection Machine? GreenArrays?
- foota 10y ago
  I think it was GreenArrays. Although in my searching Adapteva also seemed like it, but GreenArrays seems like the more likely candidate, plus it's come up more often here. I'll have to check when I get back on my desktop. Thanks much!
white-flame 10y ago
There's Tilera, and Parallella, but they're older than just a few months.
kirushik 10y ago
Multiclet? https://en.wikipedia.org/wiki/Multiclet https://en.wikipedia.org/wiki/Multiclet
qznc 10y ago
Maybe a Systolic Array thing? https://en.wikipedia.org/wiki/Systolic_array https://en.wikipedia.org/wiki/Systolic_array Maybe a Massively Parallel Processor Array thing? https://en.wikipedia.org/wiki/Massively_parallel_processor_array https://en.wikipedia.org/wiki/Massively_parallel_processor_a...
mhudson125 10y ago
Could it be the mill cpu that you were thinking about? Videos: https://www.youtube.com/channel/UCKdGg6hZoUYnjyRUb08Kjbg/ https://www.youtube.com/channel/UCKdGg6hZoUYnjyRUb08Kjbg/ The Mill CPU Architecture – The Compiler [video] (youtube.com): https://news.ycombinator.com/item?id=9856334 https://news.ycombinator.com/item?id=9856334 Wiki: https://en.wikipedia.org/wiki/Mill_CPU_Architecture https://en.wikipedia.org/wiki/Mill_CPU_Architecture
trsohmers 10y ago
Pretty sure you mean us (REX Computing; http://rexcomputing.com http://rexcomputing.com), though I would not consider our network on chip "weird" :P Our big difference that you were trying to remember was our use of scratchpad memory which is simply stated as this: We can radically reduce power consumption, increase density, and increase speed of on chip memory (SRAM) by removing the traditional hardware caching system. We instead use a purely software managed memory system, through some very fancy (or do I dare say "smart") compiler techniques that are enabled by a a very simplified architecture and the ability to guarantee latency for all memory operations. We can still have main system memory (meaning DRAM), it is just instead of having a bunch of complex hardware that burns a lot of power and wastes a lot of space in order to automatically fetch pages out of DRAM, we structure the code for each core to efficiently pull only the data necessary when it is needed.
- gnufx 10y ago
  Perhaps you've noticed the architecture of the new top top500 system. There's currently an HPC guessing game on filling in blanks in <http://www.netlib.org/utk/people/JackDongarra/PAPERS/sunway-report-2016.pdf> http://www.netlib.org/utk/people/JackDongarra/PAPERS/sunway-... but of course CPU comparisons stop at Knights Landing. One of the things I wondered about is how Linux is adapted to such an architecture. I couldn't find anything from REX on operating system support.
  - dnautics 10y ago
    I don't think you're not supposed to run linux on the current rex architecture. I think you're supposed to (pre/) compile a program for it, issue it to the chips, pass the data on over, and then sic the programs on the data.
  - trsohmers 10y ago
    Yep, have seen it... it seems to not be exactly what was described by the Chinese at ISC or SC last year (their original description being much more in line with a DSP), though there is not much data available. All of the articles I am seeing today are calling it DEC Alpha "like", though the only real source for this seems to be the wikipedia article for the family of processors, with the latest version being in 2013. Dongarra even specifically says in the paper you linked that it was NOT related to the Alpha ISA, so it seems like all of the media articles are incorrect ;) As for REX, as dnautics said, we've been mostly focused on running raw compute kernels on the current simulated versions (software and FPGA), and for the soon to be in hand silicon (coming this fall)... one of our projects internally is to port the L4 microkernel, and a telecom focused RTOS, but that is as far as our operating systems plans go for the near future. I'd also love to get a Plan 9/inferno demo running on it for fun, but we've got more important work to do at the moment.

by foota 10y ago

jacquesm 10y ago

Sutherlands 'Fleet'?

foota 10y ago
Doesn't look like it... there was an established website for the project. It seemed to have some big names from processor design and such behind it as well (at least from what I gathered on their wikipedia pages ;) ) For future reference, here is a link talking about the arch mentioned so that no one else has to wade through google's results for "fleet architecture": http://arc.cecs.pdx.edu/publications http://arc.cecs.pdx.edu/publications edit: previous (2009) discussion about fleet: https://news.ycombinator.com/item?id=723882 https://news.ycombinator.com/item?id=723882
- jacquesm 10y ago
  That one?: https://news.ycombinator.com/item?id=11845698 https://news.ycombinator.com/item?id=11845698

elij 10y ago

Maybe this? https://news.ycombinator.com/item?id=11845698 https://news.ycombinator.com/item?id=11845698

foota 10y ago
No :/ Thank you both for your suggestions though, they are appreciated :) If it helps it had the same sort of feel as the Mill architecture, in that it was a small project being developed by very enthusiastic people.
- dnautics 10y ago
  Rex computing neo chip? I know the founders and did a bit of contract work (virtual hve) on it and I think they wouldn't like being compared to mill :)

jsnell 10y ago

Could be a number of things. The Connection Machine? GreenArrays?

foota 10y ago
I think it was GreenArrays. Although in my searching Adapteva also seemed like it, but GreenArrays seems like the more likely candidate, plus it's come up more often here. I'll have to check when I get back on my desktop. Thanks much!

white-flame 10y ago

There's Tilera, and Parallella, but they're older than just a few months.

kirushik 10y ago

Multiclet? https://en.wikipedia.org/wiki/Multiclet https://en.wikipedia.org/wiki/Multiclet

qznc 10y ago

Maybe a Systolic Array thing? https://en.wikipedia.org/wiki/Systolic_array https://en.wikipedia.org/wiki/Systolic_array Maybe a Massively Parallel Processor Array thing? https://en.wikipedia.org/wiki/Massively_parallel_processor_array https://en.wikipedia.org/wiki/Massively_parallel_processor_a...

mhudson125 10y ago

Could it be the mill cpu that you were thinking about? Videos: https://www.youtube.com/channel/UCKdGg6hZoUYnjyRUb08Kjbg/ https://www.youtube.com/channel/UCKdGg6hZoUYnjyRUb08Kjbg/ The Mill CPU Architecture – The Compiler [video] (youtube.com): https://news.ycombinator.com/item?id=9856334 https://news.ycombinator.com/item?id=9856334 Wiki: https://en.wikipedia.org/wiki/Mill_CPU_Architecture https://en.wikipedia.org/wiki/Mill_CPU_Architecture

trsohmers 10y ago

Pretty sure you mean us (REX Computing; http://rexcomputing.com http://rexcomputing.com), though I would not consider our network on chip "weird" :P Our big difference that you were trying to remember was our use of scratchpad memory which is simply stated as this: We can radically reduce power consumption, increase density, and increase speed of on chip memory (SRAM) by removing the traditional hardware caching system. We instead use a purely software managed memory system, through some very fancy (or do I dare say "smart") compiler techniques that are enabled by a a very simplified architecture and the ability to guarantee latency for all memory operations. We can still have main system memory (meaning DRAM), it is just instead of having a bunch of complex hardware that burns a lot of power and wastes a lot of space in order to automatically fetch pages out of DRAM, we structure the code for each core to efficiently pull only the data necessary when it is needed.

gnufx 10y ago
Perhaps you've noticed the architecture of the new top top500 system. There's currently an HPC guessing game on filling in blanks in <http://www.netlib.org/utk/people/JackDongarra/PAPERS/sunway-report-2016.pdf> http://www.netlib.org/utk/people/JackDongarra/PAPERS/sunway-... but of course CPU comparisons stop at Knights Landing. One of the things I wondered about is how Linux is adapted to such an architecture. I couldn't find anything from REX on operating system support.
- dnautics 10y ago
  I don't think you're not supposed to run linux on the current rex architecture. I think you're supposed to (pre/) compile a program for it, issue it to the chips, pass the data on over, and then sic the programs on the data.
- trsohmers 10y ago
  Yep, have seen it... it seems to not be exactly what was described by the Chinese at ISC or SC last year (their original description being much more in line with a DSP), though there is not much data available. All of the articles I am seeing today are calling it DEC Alpha "like", though the only real source for this seems to be the wikipedia article for the family of processors, with the latest version being in 2013. Dongarra even specifically says in the paper you linked that it was NOT related to the Alpha ISA, so it seems like all of the media articles are incorrect ;) As for REX, as dnautics said, we've been mostly focused on running raw compute kernels on the current simulated versions (software and FPGA), and for the soon to be in hand silicon (coming this fall)... one of our projects internally is to port the L4 microkernel, and a telecom focused RTOS, but that is as far as our operating systems plans go for the near future. I'd also love to get a Plan 9/inferno demo running on it for fun, but we've got more important work to do at the moment.