Yeah, it'd not be very nice when DMA start bit in some DMA control register is poked before DMA address is still unset! Those architectures that do this typica

Yeah, it'd not be very nice when DMA start bit in some DMA control register is poked before DMA address is still unset! Those architectures that do this typically provide specialized always serialized instructions for communicating with memory mapped devices. If not, you need to have proper fences to ensure right order. X86 stores are always in order (except for some specific instructions, but they're no concern in this context), so it doesn't need this.