So it wasn't clear to me initially which phase of cpu development you meant. I agree with your statement regarding cpu development in the 90s. Looking at the pe

So it wasn't clear to me initially which phase of cpu development you meant. I agree with your statement regarding cpu development in the 90s. Looking at the performance equation I gave earlier, the second portion has gone from several 10s of cycles/instruction in the 486 timeframe to 2-3 INSTRUCTIONS/cycle for the Pentium III. My point was that your statement about 90% of the gains being from Instructions/clock (ie. architecture) was not always true. The Pentium 4 being a prime candidate, where the number of pipestages was dramatically scaled up (reducing instructions/clock) to increase frequency. WRT cost/die: Cpus are created on circular silicon wafers. http://arstechnica.com/hardware/news/2008/09/moore.ars/2 http://arstechnica.com/hardware/news/2008/09/moore.ars/2 Every move to a lower process node, reduces the area for each cpu die. For a given cpu, this means that more of them can be added to each wafer, driving down the cost for each unit. Ofcourse, as you mentioned, by keeping die size a constant , they get get more transistors/die, allowing them to cram more features on a chip. Lowering costs v/s adding features is a tradeoff that every cpu design team has to make.