4 ms·

Datacenter operators pay attention to cost of ownership per increment of performance. They'll be very interested in faster chips but only when they can run an

Datacenter operators pay attention to cost of ownership per increment of performance. They'll be very interested in faster chips but only when they can run an extra virtual instance on each server without raising power and cooling costs, for example. On clock speeds you're mistaken. Yes, Intel went from 20 to 1000 MHz during the nineties, and their marketing was all about clocks. But during that period, they also added 20-stage pipelines, out-of-order execution, 3 levels of caching for instructions and data, branch prediction, and hyperthreading. That's the substance of the Hennesy and Patterson claim: during the 10-year up-clocking binge, 90% of performance gains still came from architecture. I'm not sure I understand what you mean about cost per die. Can you elaborate?

skmurphy 17y ago
I think cost per die relates to wafer size, moving to 300mm wafers gave them not only many more total die but many more good die per wafer. Given that they were going to completely change out the fab equipment to support the new wafer size it made sense to move to a new process at the same time.
newfolder09 17y ago
So it wasn't clear to me initially which phase of cpu development you meant. I agree with your statement regarding cpu development in the 90s. Looking at the performance equation I gave earlier, the second portion has gone from several 10s of cycles/instruction in the 486 timeframe to 2-3 INSTRUCTIONS/cycle for the Pentium III. My point was that your statement about 90% of the gains being from Instructions/clock (ie. architecture) was not always true. The Pentium 4 being a prime candidate, where the number of pipestages was dramatically scaled up (reducing instructions/clock) to increase frequency. WRT cost/die: Cpus are created on circular silicon wafers. http://arstechnica.com/hardware/news/2008/09/moore.ars/2 http://arstechnica.com/hardware/news/2008/09/moore.ars/2 Every move to a lower process node, reduces the area for each cpu die. For a given cpu, this means that more of them can be added to each wafer, driving down the cost for each unit. Ofcourse, as you mentioned, by keeping die size a constant , they get get more transistors/die, allowing them to cram more features on a chip. Lowering costs v/s adding features is a tradeoff that every cpu design team has to make.

skmurphy 17y ago

I think cost per die relates to wafer size, moving to 300mm wafers gave them not only many more total die but many more good die per wafer. Given that they were going to completely change out the fab equipment to support the new wafer size it made sense to move to a new process at the same time.

newfolder09 17y ago

So it wasn't clear to me initially which phase of cpu development you meant. I agree with your statement regarding cpu development in the 90s. Looking at the performance equation I gave earlier, the second portion has gone from several 10s of cycles/instruction in the 486 timeframe to 2-3 INSTRUCTIONS/cycle for the Pentium III. My point was that your statement about 90% of the gains being from Instructions/clock (ie. architecture) was not always true. The Pentium 4 being a prime candidate, where the number of pipestages was dramatically scaled up (reducing instructions/clock) to increase frequency. WRT cost/die: Cpus are created on circular silicon wafers. http://arstechnica.com/hardware/news/2008/09/moore.ars/2 http://arstechnica.com/hardware/news/2008/09/moore.ars/2 Every move to a lower process node, reduces the area for each cpu die. For a given cpu, this means that more of them can be added to each wafer, driving down the cost for each unit. Ofcourse, as you mentioned, by keeping die size a constant , they get get more transistors/die, allowing them to cram more features on a chip. Lowering costs v/s adding features is a tradeoff that every cpu design team has to make.