3 ms·
Great article. Interesting that modifying and reading word-sized values is an atomic operation on ARM. IIRC on x86 this is not the case because values can be ca
by bwindels 10y ago
Great article. Interesting that modifying and reading word-sized values is an atomic operation on ARM. IIRC on x86 this is not the case because values can be cached on the cache of the different cpu cores, and thus be out of sync. Does someone have a more detailed insight into this?
- biokoda 10y ago> and thus be out of sync The operation is still atomic. You will not get a partially written word size value.
- AstralStorm 10y agoARMv7 works on deferred consistency between cores and memory. So, even if the write itself is "atomic", which should rather be called tear-free, there is no inherent synchronisation of writes and reads to the same memory location. C11 and C++11 atomics also guarantee ordering depending on the memory model parameter. Look up Sutter's talk titled "Atomic Weapons" for more detail.
- bwindels 10y agoInteresting talk! Here's the link: https://channel9.msdn.com/Shows/Going+Deep/Cpp-and-Beyond-2012-Herb-Sutter-atomic-Weapons-1-of-2 https://channel9.msdn.com/Shows/Going+Deep/Cpp-and-Beyond-20...
- stplsd 10y agohttps://lagunita.stanford.edu/c4x/Engineering/CS316/asset/A_Primer_on_Memory_Consistency_and_Coherence.pdf https://lagunita.stanford.edu/c4x/Engineering/CS316/asset/A_...