Most CPU architectures have instructions to zero memory, but whether its a single instructions or a few in a loop doesn't make much of a difference [1], since t

Most CPU architectures have instructions to zero memory, but whether its a single instructions or a few in a loop doesn't make much of a difference [1], since the problem is that the underlying memory is dog slow in comparison. If you want better hardware support, you need to keep the memory hierarchy in mind, and recall that there are multiple coherent masters in any modern system. If we teach DRAM to zero a block on command, the CPU can't just ask DRAM to do that - the L1, L2 and L3 caches need to be kept coherent, and the other CPUs have their own L1 caches too. We could teach DDR to accept "write zeros" commands from L3, and L3 to accept them from L2, and L2 to accept them from L1. L1 is already accepting them from the CPUs that have memory-zeroing instructions. In fact I'm aware of one CPU design where that already exists in the L1<->L2 interface [2]. One could also take a different approach - if you assume the kernel wants to keep the memory on the free-list zero'd, then you could have another coherent master in the memory system to do that work for the kernel. When a page is de-allocated, the kernel hands it to the memory zero-er, when the zero-er is done, it fires an interrupt and the kernel accepts the page onto the free list. I'll bet there are a lot of DMA controllers that could be made to do this already, although I don't know if any of them could do it fast enough to be a net win given the extra interrupt activity. [1]: Except on some embedded CPUs, which can manage caches more efficiently when using memory-zeroing instructions. [2]: http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/ric1447333697057.html http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401...