care to give an example? I've worked plenty with HDLs (mainly system verilog) from large ASIC projects to smaller FPGA prototyping projects. I could guess at

care to give an example? I've worked plenty with HDLs (mainly system verilog) from large ASIC projects to smaller FPGA prototyping projects. I could guess at a couple ways these new HDLs could possibly address some of the pain points, but it's not clear that's even their purpose.