As others have pointed out, there are several factors. One is that defects in silicon tend to exist in a given areal density. Which means that for a given wafer

As others have pointed out, there are several factors. One is that defects in silicon tend to exist in a given areal density. Which means that for a given wafer you'll have, on average, a certain number of defects for a given process, and that in turn translates to the same number of defective chips from that wafer. The more total chips you cram on a wafer then the higher the percentage of non-defective chips you'll get, more or less. Additionally, smaller chips typically mean faster and lower power chips. Overall these are very very strong factors which push towards shrinking chip size at every opportunity.