4 ms·
You should read the paper, all of this was considered.
by impdmnt2Prgrss 10y ago
You should read the paper, all of this was considered.
- esmi 10y agoI agree it's unfair to say modern testing techniques were totally ignored but I think many standard techniques were not considered. For example, they dismissed the idea of filling empty space. I think this is easily achieved. Post place and route go find all empty space and fill it with scan flops. If you need something smaller put inverters between them. Tap into the chain in vicinity of the void and to minimize route impact. At test, scan through a random bit pattern. This will ensure all flops are present as I can determine the chain depth and all bits of the string must be retained. I also am critical of the need to test against golden references as I can just compare against the CAD. I've personally designed scan TD vectors which found one weak buffer incorrectly selected by the mapper and I didn't know the problem was a weak buffer when I started. I think this is equivalent to loading the net with extra gates. On process attacks, process monitoring circuits exist. I can verify them with external equipment on an analog test bus which is how we DV them. I definitely think the paper is very good and I will go through it in more detail when I have time but I also think they are too quick to dismiss the defenses and I don't think their defense list is exhaustive. I should also mention, this is my opinion on detecting circuits inserted in parallel to a given design. If the attacker is allowed to modify the design directly... Then all bets are off. :)