Oh sure, you could do a ring bus and it'll scale for workloads that aren't the ones Intel targets for their CPUs. (General purpose, not vector, not SIMD, just

Oh sure, you could do a ring bus and it'll scale for workloads that aren't the ones Intel targets for their CPUs. (General purpose, not vector, not SIMD, just straight-up random computations requesting all kinds of data from all kinds of places.) I think they'll drop the rings soon. But it will keep them going until they figure out how to solve their interconnect problems. I agree with you that the SON as on RAW/Tilera is unlikely to make the leap to Intel. I just hope they'll move towards that direction. Though clearly they may also chose to move in a completely different direction, but they will need a more sensible strategy than they've got now and I really doubt it's going to be rings for the type of straight up make no assumptions about your workload general computing Intel must be good at. We don't agree that on-chip networks aren't important though. While right now no one's got a good programming model for these things, we're going to need one and there's likely going to be some data sharing involved, which means a good on-chip network is going to be a hell of a thing. Also I simply don't envision a cache architecture that makes sense that doesn't have a lot of unfortunate on-chip communication, and that needs to not be annoyingly NUMA. (Though it may have to be to some degree...) I guess we'll find out. :) And as an aside, thanks for taking the time to provide one of the more informative and responsive posts attached to this thread. I think HN could use more architecture folks.