France is the most VHDL country in the world. Hopefully VHDL dies a terrible death and SystemVerilog becomes the defacto standard, which it is already well on

France is the most VHDL country in the world. Hopefully VHDL dies a terrible death and SystemVerilog becomes the defacto standard, which it is already well on its way of becoming. It is way more powerful, especially for Verification. UVM is now the one true standard for verification.