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My impression was more Verilog in academia, VHDL in industry.
by mnw21cam 10y ago
My impression was more Verilog in academia, VHDL in industry.
- krupan 10y agoMy impression is VHDL for defense contractors, verilog for commercial.
- tremon 10y agoI did VHDL in academia, in Europe.
- BooneJS 10y agoThere's very little VHDL in industry. VHDL == IBM and Europe.
- typon 10y agoFrance is the most VHDL country in the world. Hopefully VHDL dies a terrible death and SystemVerilog becomes the defacto standard, which it is already well on its way of becoming. It is way more powerful, especially for Verification. UVM is now the one true standard for verification.