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Sounds like UC Berkely is doing something similar to Clash with Chisel, except written in Scala instead of Haskell. Not sure which offers greater bang for the b
by virtualwhys 10y ago
Sounds like UC Berkely is doing something similar to Clash with Chisel, except written in Scala instead of Haskell. Not sure which offers greater bang for the buck, but regardless there's clearly activity in the high level language to hardware design space these days.
[1] https://chisel.eecs.berkeley.edu/faq.html https://chisel.eecs.berkeley.edu/faq.html
[2] https://chisel.eecs.berkeley.edu/index.html https://chisel.eecs.berkeley.edu/index.html
- Cyph0n 10y agoYes, Chisel is quite interesting and seems to have significant backing from UCB. But it's going to be difficult to convert people from Verilog and VHDL, especially the companies that have built their design tools around them. Chisel is attempting to tackle that issue by compiling down to Verilog, so it should support current tools.
- typon 10y agoSo does Clash. The problem is that the generated RTL is not particularly readable. This is a huge deal when debugging your RTL in a simulator. Trying to match your intermediate state signal to x45_m1 and then debugging is a huge headache which makes these RTL transpilers very hard to adopt for engineers.
- Ericson2314 10y agoIt's true. Thank goodness most things can be caught before compilation.