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From the article: "TPU is tailored to machine learning applications, allowing the chip to be more tolerant of reduced computational precision, which means it re
by BooneJS 10y ago
From the article: "TPU is tailored to machine learning applications, allowing the chip to be more tolerant of reduced computational precision, which means it requires fewer transistors per operation."
- euyyn 10y agoDo you reckon that means it's using small floats?
- protomok 10y agoBased on recent blog posts from some Google folks regarding quantizing neural nets I'm going to guess 8-bit fixed point. For example -> https://petewarden.com/2016/05/03/how-to-quantize-neural-networks-with-tensorflow https://petewarden.com/2016/05/03/how-to-quantize-neural-net...
- pygy_ 10y agoOr small ints, possibly working in log space.
- nhaehnle 10y agoProbably. In addition, there's a lot of literature on optimizing hardware implementations of fundamental arithmetic operations like addition and multiplication. I recall seeing a paper a while ago which talked about reducing the number of gates by allowing some bounded imprecision in the results - unfortunately, I don't remember the title right now, but it sounds like that's what they may be doing.
- tcarey83 10y agoWhen I first read the blog post earlier in the day, it actually said they were using 8-bits. I remember it because it seem quite small to me.