This, a thousand times. If you want minimum latency, FPGAs are of course a possible solution, but selling it as a "better C++" is just laughable. When you have

This, a thousand times. If you want minimum latency, FPGAs are of course a possible solution, but selling it as a "better C++" is just laughable. When you have an IP core which fits your problem, then by all means use it (and hope it works as advertised), but otherwise: the less you need to do in an FPGA, the better.