4 ms·

Is there something like SPARC or other RISC architectures?

userbinator 11y ago
Yes there are... I wouldn't recommend starting with SPARC Asm though, it's nowhere near as fun as a CISC like x86, nor as easy as MIPS (which tends to be the "boring" go-to architecture CS courses use.) ARM is more interesting than MIPS and easier than x86.
- ae_keji 11y ago
  What do you mean by ARM being more interesting than MIPS?
  - kabdib 11y ago
    - More ARM systems shipping today than MIPs - The ARM has a standard MMU (well, two major revs). MIPs has quite a few variants, and they involve TLB invalidation / reload. They're both worth working with. - ARM has made some interesting architectural choices over the years, and it's worth studying what they've done. MIPs is more a static platform, not as much market pressure or will to innovate.
- gravypod 11y ago
  I've done a little bit of x86 and I have to say I'm not very impressed by some of it. It seems like the lowest common denominator where nothing 'fun' happened. ARM has a few ecosystem problems that I'd rather not deal with. From what I understand there is a lack of hardware discovery. ARM is more embedded then 'user' computer. Nothing is swapable.
  - userbinator 11y ago
    You might find these size-optimisation challenges more fun: http://www.hugi.scene.org/compo/compoold.htm http://www.hugi.scene.org/compo/compoold.htm The 256B and below categories in the demoscene are also sources of interesting x86 Asm programs: https://news.ycombinator.com/item?id=7960358 https://news.ycombinator.com/item?id=7960358
signa11 11y ago
> other RISC architecture... For mips there is an excellent book called 'see mips run' by dominic-sweetman. you might find it to be quite instructive...
Annatar 11y ago
Yes, The SPARC architecture manual. Punch that into Google or DuckDuckGo and it should be the second link (you want the SPARC V9 instruction set architecture). I would post the link I found, but since I actually have the physical book, I'm uncertain as to whether posting a link to a PDF of a possibly copyrighted book would get me in trouble with Hacker News or not. I've done some SPARC assembler programming for fun, and for someone with 6502 / MC680x0 assembler background, SPARC has a really exotic assembler (register windows and synthetic instructions, most notably). It also illustrates just how complex and powerful the Scalable Processor ARCitecture is; for a RISC CPU, it has loads and loads of advanced features all designed for high performance, which leads me to think that the existing compilers generating SPARC code must be crap, since some of the SPARC processors (notably UltraSPARC II, UltraSPARC III, and UltraSPARC T1) are generally known to be slow when it comes to non-parallelized, number crunching performance. The design of the SPARC processors and their assembler is in direct opposition to that.
- gravypod 11y ago
  How much does the hard copy run you? I am thinking of porting my hobby OS to the architecture so it's probably worth having around in hard copy form.
  - Annatar 11y ago
    Prices vary. I might have bought it new off of Amazon for $90, but I don't remember any more. http://www.amazon.com/SPARC-Architecture-Manual-Version9-International/dp/0130992275/ http://www.amazon.com/SPARC-Architecture-Manual-Version9-Int...
- userbinator 11y ago
  It shouldn't be a problem to link to it, because you can find a newer version of it sitting on Oracle's site as well as SPARC's official site: http://sparc.org/technical-documents/specifications/ http://sparc.org/technical-documents/specifications/ are generally known to be slow when it comes to non-parallelized, number crunching performance I think that's due to a similar set of design decisions that lead to the Itanium also being an amazing benchmark performer, but dismal in "general purpose" code. IMHO SPARC and Itanium are architectures that have optimised heavily for the sort of massively parallel, predictable/few branches, predictable-memory-access-pattern that "high performance computing" benchmarks show off, but at the expense of the small, branchy, less predictable "serial byte/bit manipulation" that tends to be common in other, more general-purpose code. To use a car analogy, it's like a dragster vs. a rally car.
ericbb 11y ago
See the RISC-V User-Level ISA Specification v2.0 [1]. It's more detailed but still fairly easy reading. [1] http://riscv.org/specifications/ http://riscv.org/specifications/

Yes there are... I wouldn't recommend starting with SPARC Asm though, it's nowhere near as fun as a CISC like x86, nor as easy as MIPS (which tends to be the "boring" go-to architecture CS courses use.) ARM is more interesting than MIPS and easier than x86.

ae_keji 11y ago
What do you mean by ARM being more interesting than MIPS?
- kabdib 11y ago
  - More ARM systems shipping today than MIPs - The ARM has a standard MMU (well, two major revs). MIPs has quite a few variants, and they involve TLB invalidation / reload. They're both worth working with. - ARM has made some interesting architectural choices over the years, and it's worth studying what they've done. MIPs is more a static platform, not as much market pressure or will to innovate.
gravypod 11y ago
I've done a little bit of x86 and I have to say I'm not very impressed by some of it. It seems like the lowest common denominator where nothing 'fun' happened. ARM has a few ecosystem problems that I'd rather not deal with. From what I understand there is a lack of hardware discovery. ARM is more embedded then 'user' computer. Nothing is swapable.
- userbinator 11y ago
  You might find these size-optimisation challenges more fun: http://www.hugi.scene.org/compo/compoold.htm http://www.hugi.scene.org/compo/compoold.htm The 256B and below categories in the demoscene are also sources of interesting x86 Asm programs: https://news.ycombinator.com/item?id=7960358 https://news.ycombinator.com/item?id=7960358

signa11 11y ago

> other RISC architecture... For mips there is an excellent book called 'see mips run' by dominic-sweetman. you might find it to be quite instructive...

Annatar 11y ago

Yes, The SPARC architecture manual. Punch that into Google or DuckDuckGo and it should be the second link (you want the SPARC V9 instruction set architecture). I would post the link I found, but since I actually have the physical book, I'm uncertain as to whether posting a link to a PDF of a possibly copyrighted book would get me in trouble with Hacker News or not. I've done some SPARC assembler programming for fun, and for someone with 6502 / MC680x0 assembler background, SPARC has a really exotic assembler (register windows and synthetic instructions, most notably). It also illustrates just how complex and powerful the Scalable Processor ARCitecture is; for a RISC CPU, it has loads and loads of advanced features all designed for high performance, which leads me to think that the existing compilers generating SPARC code must be crap, since some of the SPARC processors (notably UltraSPARC II, UltraSPARC III, and UltraSPARC T1) are generally known to be slow when it comes to non-parallelized, number crunching performance. The design of the SPARC processors and their assembler is in direct opposition to that.

gravypod 11y ago
How much does the hard copy run you? I am thinking of porting my hobby OS to the architecture so it's probably worth having around in hard copy form.
- Annatar 11y ago
  Prices vary. I might have bought it new off of Amazon for $90, but I don't remember any more. http://www.amazon.com/SPARC-Architecture-Manual-Version9-International/dp/0130992275/ http://www.amazon.com/SPARC-Architecture-Manual-Version9-Int...
userbinator 11y ago
It shouldn't be a problem to link to it, because you can find a newer version of it sitting on Oracle's site as well as SPARC's official site: http://sparc.org/technical-documents/specifications/ http://sparc.org/technical-documents/specifications/ are generally known to be slow when it comes to non-parallelized, number crunching performance I think that's due to a similar set of design decisions that lead to the Itanium also being an amazing benchmark performer, but dismal in "general purpose" code. IMHO SPARC and Itanium are architectures that have optimised heavily for the sort of massively parallel, predictable/few branches, predictable-memory-access-pattern that "high performance computing" benchmarks show off, but at the expense of the small, branchy, less predictable "serial byte/bit manipulation" that tends to be common in other, more general-purpose code. To use a car analogy, it's like a dragster vs. a rally car.

ericbb 11y ago

See the RISC-V User-Level ISA Specification v2.0 [1]. It's more detailed but still fairly easy reading. [1] http://riscv.org/specifications/ http://riscv.org/specifications/