4 ms·
In a word: no. Processors this simple don't implement any of the features you mention, including multi-level memory hierarchies, and I doubt the author had any
by cdkersey 10y ago
In a word: no. Processors this simple don't implement any of the features you mention, including multi-level memory hierarchies, and I doubt the author had any inclination to make the assembler self-hosting.
- Someone 10y agoI'm not saying one should expect or demand it in a project like this, but minimalistic pipelining should be doable; both the 6502 (http://www.6502.org/users/andre/65k/arch.html#pipelining http://www.6502.org/users/andre/65k/arch.html#pipelining) and (IIRC) the 8080 started fetching the next instruction before finishing execution of the current one, where possible.
- to3m 10y agoDo you have an example of a case where this provided a performance benefit to 6502 code?