4 ms·
the hardware performs some coalescing, but it's complicated... memory accesses in a warp do not necessarily have to be contiguous, but it does matter how many
by jhj 10y ago
the hardware performs some coalescing, but it's complicated...
memory accesses in a warp do not necessarily have to be contiguous, but it does matter how many 32 byte global memory segments (and 128 byte l1 cache segments) they fall into. the memory controller can load 1, 2 or 4 of those 32 byte segments in a single transaction, but that's read through the cache in 128 byte cache lines.
thus, if every lane in a warp loads a random word in a 128 byte range, then there is no penalty; it's 1 transaction and the reading is at full efficiency. but, if every lane in a warp loads 4 bytes with a stride of 128 bytes, then this is very bad: 4096 bytes are loaded but only 128 are used, resulting in ~3% efficiency.
- pandaman 10y agoThanks, this is about how I imagined all GPUs work. With most games using interleaved vertex buffers it would be a very strange decision to penalize this access pattern.
- robbies 10y agoActually...that might be changing on GCN. Check out Graham Wihlidal's presentation from this past GDC. Advocates some benefits of de-interleaved VBs http://www.wihlidal.ca/Presentations/GDC_2016_Compute.pdf http://www.wihlidal.ca/Presentations/GDC_2016_Compute.pdf
- pandaman 10y agoIt might, but most likely it won't: splitting position data from the rest of vertex had been around since, at least, PS3 (for the similar reasons of culling prims) and yet how many games have done the Edge's tri-culling in that generation? And even if you go ahead and split off position the rest of the vertex is still better be interleaved.