Power efficiency and size reduction go hand in hand. The gate capacitance is reduced at lower geometry, and you can also reduce the core voltage. Both of which

Power efficiency and size reduction go hand in hand. The gate capacitance is reduced at lower geometry, and you can also reduce the core voltage. Both of which directly contribute to power. The only other way to reduce power is by clock gating, which pretty much happens these days on any decent SoC design targeted at mobile.